Patents by Inventor Masahiko Maeda

Masahiko Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6162730
    Abstract: A method for efficiently fabricating semiconductor wafers of good planarization without utilizing chemical solutions of high etching rate is disclosed. The method slices a single-crystal ingot into slices of wafers. The edge of each wafer is chamfered. A lapping or grinding step is carried out to planarize the chamfered wafer. Both side surfaces of the wafer are then polished. Next, the wafer surface is mirror polished. Finally, the wafer is cleaned.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: December 19, 2000
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Jun-ichi Yamashita, Toshiharu Yubitani, Hirofumi Hajime, Takamitsu Harada
  • Patent number: 6066565
    Abstract: A sliced wafer 1a is obtained by cutting it off from a semiconductor ingot. The rear and front surfaces of the sliced wafer 1a are flattened by the first double side simultaneous grinding process so as to remove unevenness 12a. The ground rear and front surfaces of the sliced wafer 1a whose unevenness 12a has been removed are subject to the second double side simultaneous grinding process. The flattened back side surface of the sliced wafer 1b is sucked so as to chamfer the outer peripheral portion 1b of the sliced wafer 1b. Then, the surface of the chamfered wafer 1c is etched.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: May 23, 2000
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hideyo Kuroki, Masahiko Maeda
  • Patent number: 6043156
    Abstract: It is an object of the present invention to provide a method for efficiently making semiconductor wafers that prevents the production of metal pollution. It is another object of the present invention to provide a method where the back side of the wafer does not influence the front side, thereof, and where the front and back sides of the wafer can be distinguished are polishing.This invention provides a method for efficiently making semiconductor wafers having uniform thickness where the thickness of the back side does not influence the front side and where the front side of the wafer is capable of being distinguished from the back side. A semiconductor ingot is sliced to obtain wafers. The sliced surfaces of the wafers are flattened. The flattened wafer is etched in alkaline etching solution.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: March 28, 2000
    Assignee: Komatsu Electric Metals Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Kenji Kawate
  • Patent number: 6001007
    Abstract: A backing pad 7 is secured on the bottom of a ceramic plate 6. A template 1 is secured on the bottom of the backing pad 7. The thickness of the template 1 successively diminishes from the inner periphery wall 12 of the central accommodation opening for restraining the semiconductor wafer, toward the outer periphery wall 13 of the template 1, so that the bottom of the template 1 is inclined and the cross section of the template 1 is tapered.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: December 14, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Masahiko Maeda, Yuichi Nakayoshi
  • Patent number: 5963821
    Abstract: This invention provides a method for efficiently making semiconductor wafers having uniform thickness where the thickness of the back side does not influence the front side and where the front side of the wafer is capable of being distinguished from the back side. A semiconductor ingot is sliced to obtain wafers. The sliced surfaces of the wafers are flattened. The flattened wafer is etched in alkaline etching solution. Both the front and back sides of the etched wafer are polished using a double sided polishing apparatus so that the front side is a mirror surface and an unevenness remains on the back side to distinguish the front and back sides, thereof. The polished wafer is cleaned.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: October 5, 1999
    Assignee: Komatsu Electronic Metal Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Kenji Kawate
  • Patent number: 5904568
    Abstract: A process for precisely and efficiently manufacturing a semiconductor wafer is provided, which can prevent contamination by metals inside silicon crystals and remove the factors that degrade the GOI produced during the wafer manufacturing steps. A sliced and chamfered semiconductor wafer is subjected to lapping. The lapped semiconductor wafer is then etched, and thus the working strains produced by lapping is removed. The two sides of the etched semiconductor wafer are then primary polished with a dual-surface polishing machine. The primary polished semiconductor wafer is etched with an aqueous solution of 1% NaOH solution. The weak alkali etched semiconductor wafer is then mirror processed by a finish polishing. The finish polished semiconductor wafer is washed with an SC-1 solution.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: May 18, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Masahiko Maeda, Takamitsu Harada, Hisami Motoura, Eiichi Asano
  • Patent number: 5899731
    Abstract: A method of fabricating a semiconductor wafers, which can prevent metal contamination when alkali etching is used. A semiconductor ingot is cut into wafers. The peripheral portion of the sliced wafers is chamfered. The chamfered wafers are then planarized by lapping. The planarized wafers are alkali etched. The alkali etched wafers are subjected to acid washing by using diluted mixed acid solution. The surface of the acid-washed wafers are then polished. The polished wafers are washed again.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: May 4, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Kenji Kawate
  • Patent number: 5899743
    Abstract: A method for efficiently fabricating semiconductor wafers of good planarization without utilizing chemical solutions of high etching rate is disclosed. The method slices a single-crystal ingot into slices of wafers. The edge of each wafer is chamfered. A lapping step is carried out to planarize the chamfered wafer. Both side surfaces of the wafer are then polished. Next, the wafer surface is mirror polished. Finally, the wafer is cleaned.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: May 4, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Fumitaka Kai, Masahiko Maeda, Jun-ichi Yamashita, Toshiharu Yubitani, Hirofumi Hajime, Takamitsu Harada
  • Patent number: 5849636
    Abstract: A method processes a semiconductor wafer by etching the wafer, which has been smoothed by rough lapping, with alkaline solution. A rod is sliced into a plurality of wafers. The peripheral edges of the wafers are chamfered. The processed strain layers over the wafers due to chamfering are smoothed and planarized. The processed strain layers are then removed by etching with alkaline solution. The etched wafers are mirror polished. Lastly, the mirror-polished wafers are cleaned.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: December 15, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Takamitsu Harada, Kouichi Imura, Hisaya Fukunaga, Masahiko Maeda
  • Patent number: 5747364
    Abstract: A method of making semiconductor wafers can prevent processing strain on peripheral portions of wafers caused by non-wax polishing using a template. This involves mirror chamfering or etching the peripheral portions of the wafers after the non-wax polishing step.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: May 5, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Nobuyuki Akiyama, Fumitaka Kai, Masahiko Maeda, Hirofumi Hajime, Naoki Yamada
  • Patent number: 5737676
    Abstract: A latent electrostatic image developing device for use in developing a latent electrostatic image to a toner image in an image forming machine. The device includes a developing roller within a development housing for holding a developer on its surface in a developer holding zone and conveying the developer, which is held to a developing zone, in order to apply it to a latent electrostatic image. A restricting portion has a blade which includes a rigid part for acting on the surface of the developing roller in a developer restricting zone located between the developer holding zone and the developing zone in order to restrict the amount of the developer held on the surface. The blade is caused to protrude to the upstream side as viewed in the direction of movement of the developing roller, and that border of its protrusion facing the developing roller is provided with a C 0.1 to 0.6 mm chamfer (C being the JIS designation for a 45 degree chamfer).
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: April 7, 1998
    Assignee: Mita Industrial
    Inventors: Masahiko Maeda, Masayuki Nakashima, Masao Uyama, Shoji Tomita, Kenichiro Kitajima
  • Patent number: 5685880
    Abstract: A leather modifier containing a compound which is obtainable through a reaction of an ethylene oxide derivative having a fluorine-containing group with a phosphorus compound is disclosed. A leather treated with the modifier has much improved properties.
    Type: Grant
    Filed: April 21, 1994
    Date of Patent: November 11, 1997
    Assignee: Daikin Industries, Ltd.
    Inventors: Tetsuya Masutani, Masato Kuroi, Yasuo Itami, Masahiko Maeda, Norio Yanagisawa, Yoshihiko Misugi, Maki Yasuhara
  • Patent number: 5557380
    Abstract: An apparatus for developing an electrostatic latent image includes a developing agent application device which holds the developing agent on the surface thereof in the developing agent-holding zone, and conveys the thus held developing agent into a developing zone to apply it onto the electrostatic latent image. A limiting device is included for limiting the amount of the developing agent held on the surface of the developing agent application device in a developing agent limiting zone located between the developing agent holding zone and the developing zone. The limiting device includes a blade made of a rigid member that is brought into forced contact with the surface of the developing agent application device, a blade support device for supporting the blade in a manner such that a first surface thereof is forced into contact with the surface of the developing agent application device, and a resilient urging device which is disposed on a side of a second surface of the blade.
    Type: Grant
    Filed: June 20, 1995
    Date of Patent: September 17, 1996
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Masahiko Maeda, Shoji Tomita, Masao Uyama, Masayuki Nakashima, Kenichiro Kitajima
  • Patent number: 5530525
    Abstract: An image forming apparatus includes a charge removing device for removing the residual charge on a photosensitive film. The light emitted from an optical source of the charge removing device is selected from the range between the wavelengths which correspond to half of the maximum absorbance in a light absorbance characteristic of the photosensitive film. Since carrier generation does not occur by the light emitted by the charge removing device, the charging ability and the charge retaining ability of the photosensitive film are improved, and the image quality is significantly improved.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: June 25, 1996
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Mitsuji Tsujita, Masahiko Maeda, Kazuhiro Mizude, Tomohiro Tsutano, Masao Uyama, Nariaki Tanaka, Takashi Terada, Takuji Terada
  • Patent number: 5450176
    Abstract: An apparatus for developing an electrostatic latent image which includes a developing agent application assembly and a limiting device for limiting the amount of the developing agent held on the surface of the developing agent application assembly. The limiting device is made of a rigid member such as a sheet glass and its one surface is brought into forced contact with the surface of the developing agent application assembly.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: September 12, 1995
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Kouji Unemo, Masahiko Maeda, Shoji Tomita, Masao Uyama, Masayuki Nakashima
  • Patent number: 5268718
    Abstract: A developing device constructed such that a rotational axis of a transmission gear which is engaged with a gear attached to the photosensitive drum of an image forming apparatus is fixed in relation the photosensitive drum gear in order to transmit the rotational force of the photosensitive drum to the developing roller via gears, and at the same time the transmission gear axis is rockably suspended and supported as a supporting axis of the developing unit, the developing roller gear is linked with a transmission gear by means of a plurality of gears, and a force which acts to keep the developing unit away from the photosensitive drum is decreased.
    Type: Grant
    Filed: May 12, 1992
    Date of Patent: December 7, 1993
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Masahiko Maeda, Kisaku Koshijima, Masao Uyama
  • Patent number: 5268811
    Abstract: A refrigerator controller which can positively lock and unlock a door thereof in accordance with a command signal from a host-computer connected therewith. The refrigerator controller includes a power supply voltage indicating device. A DC power supply is charged by a DC power source and energizes a door lock mechanism activating device to lock and unlock the door. DC voltage generated by the DC power supply rises as it is charged by the DC power source. The door lock mechanism activating device can be energized to positively lock and unlock the door by being fed with a predetermined lower limit voltage. Only when the DC voltage generated by the DC power supply is no lower than the predetermined lower limit voltage is the door lock mechanism activating device energized by the DC power supply to lock and unlock the door of the refrigerator in accordance with the command signal.
    Type: Grant
    Filed: December 9, 1991
    Date of Patent: December 7, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiko Maeda
  • Patent number: 5256318
    Abstract: A tanned leather treated with a fatliquoring agent in combination with a fluorine-containing oil, which has good touch, water resistance, water- and oil-repellency, washing resistance, and which is not discolored or faded by dry cleaning.
    Type: Grant
    Filed: April 3, 1991
    Date of Patent: October 26, 1993
    Assignee: Daikin Industries Ltd.
    Inventors: Tetsuya Masutani, Masahiko Maeda, Norio Yanagisawa, Masato Kuroi
  • Patent number: 5166472
    Abstract: A developing device which includes a housing including an opening toward a photosensitive drum, the housing containing a single-component toner, a developing roller disposed in the opening facing the photosensitive drum so as to transfer the toner to an image-forming area between the developing roller and the photosensitive drum, a porous plate disposed in the opening and kept in contact with the part of the developing roller which is positioned in the housing, the porous plate having pores of such a size so as to allow the toner to pass through, and a toner supply means for supplying the toner from the housing to the porous plate.
    Type: Grant
    Filed: August 1, 1991
    Date of Patent: November 24, 1992
    Assignee: Mita Industrial Co., Ltd.
    Inventors: Masahiko Maeda, Yasuhiro Koshijima, deceased, Osamu Takemura
  • Patent number: 5142254
    Abstract: An ultrasonic delay line device has an adjusting circuit for adjusting delay time provided between two terminals at the power input side of an ultrasonic delay line, wherein the adjusting circuit includes a serial connection of a fixed capacitor and a variable resistor connected between said two terminals of the power input side and a fixed coil connected in parallel with the serial connection of the fixed capacitor and the variable resistor.
    Type: Grant
    Filed: August 31, 1990
    Date of Patent: August 25, 1992
    Assignee: Asahi Glass Company Ltd.
    Inventors: Etsuji Kimura, Naomitsu Umemura, Masahiko Maeda