Patents by Inventor Masahiko Nakamizo
Masahiko Nakamizo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8576156Abstract: An auxiliary capacitor line driving circuit (5), provided in a surrounding region located around a display region (R1) in a liquid crystal display panel, generates auxiliary capacitor driving signals, and includes: first and second voltage trunk lines (VCS1, VCS2) which carry two different voltages, respectively; at least one control signal line (VCTRL1, VCTRL2) carrying one control signal; and a plurality of TFTs (T1, T2, T3, T4) each alternately supplying, to the respective auxiliary capacitor lines (CSn, CSn+1, and the like) in a given cycle, the two different voltages supplied to the auxiliary capacitor line driving circuit (5). Therefore, a liquid crystal display device employing multi-picture element drive method can be provided as a liquid crystal display device that achieves narrowing of a picture frame region as a non-display region and an external circuit board.Type: GrantFiled: November 26, 2010Date of Patent: November 5, 2013Assignee: Sharp Kabushiki KaishaInventors: Masahiko Nakamizo, Akihiro Shohraku
-
Publication number: 20130207884Abstract: A display device 10 according to the present invention includes a plurality of pixels 40 each including a plurality of sub pixels 42, a plurality of auxiliary capacitance lines 36 forming an auxiliary capacitance 56 with the sub pixels 42, and an auxiliary capacitance driver 34 configured to supply an auxiliary capacitance drive signal to the auxiliary capacitance lines 36 and to apply a voltage to the auxiliary capacitance. In the display device 10, the auxiliary capacitance driver 34 includes a plurality of connection terminals 64 each connected to each of the auxiliary capacitance lines 36.Type: ApplicationFiled: October 26, 2011Publication date: August 15, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Masahiko Nakamizo, Fumikazu Shimoshikiryoh, Takamitsu Suzuki, Akifumi Hashimoto
-
Patent number: 8422622Abstract: To provide a shift register and a display device each capable of satisfactorily preventing noises of individual stage outputs without increasing circuit complexity, each stage of the shift register includes: a first output transistor; a first capacitor; an input gate; a first switching element; a second switching element; a third switching element; a fourth switching element; and a fifth switching element.Type: GrantFiled: February 24, 2010Date of Patent: April 16, 2013Assignee: Sharp Kabushiki KaishaInventors: Masahiko Nakamizo, Masashi Yonemaru, Yasuaki Iwase, Kenichi Ishii
-
Publication number: 20130069930Abstract: A bistable circuit includes an output terminal that outputs a state signal, an output terminal that outputs an other-stage control signal, a first node of which a potential is controlled based on a set signal and a clear signal, a thin-film transistor that provides a potential of a second clock to the output terminal when a potential of the first node is at a high level, a thin-film transistor that provides a potential of a first clock to the output terminal when a potential of the first node is at a high level, and a thin-film transistor for changing a potential of the other-stage control signal to a low level based on a reset signal. The first clock is generated by a power source of a different system from the second clock, and has a smaller amplitude than that of the second clock.Type: ApplicationFiled: October 29, 2010Publication date: March 21, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Tetsuo Fukaya, Masashi Yonemaru, Kenichi Ishii, Masahiko Nakamizo
-
Patent number: 8384461Abstract: Disclosed are a shift register and a display device which can suppress noise of output of each stage without causing an increase in circuit scale. In at least one example embodiment, each stage of the shift register includes a first output transistor, a second output transistor, a first capacitor, a second capacitor, an input gate, a first switching element, a second switching element, a third switching element, a fourth switching element, and a fifth switching element.Type: GrantFiled: February 22, 2010Date of Patent: February 26, 2013Assignee: Sharp Kabushiki KaishaInventors: Masashi Yonemaru, Masahiko Nakamizo
-
Publication number: 20130044854Abstract: Each stage of a shift register includes: a shift pulse input terminal; a shift pulse output terminal; first to fifth terminals; an input gate, first to fourth switching elements; a first output transistor, and a first circuit, connected between a first output terminal and the second input terminal, which forms a current path between the first output terminal and the second input terminal.Type: ApplicationFiled: November 11, 2010Publication date: February 21, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Masashi Yonemaru, Masahiko Nakamizo, Yasuaki Iwase
-
Publication number: 20130009934Abstract: An auxiliary capacitor line driving circuit (5), provided in a surrounding region located around a display region (R1) in a liquid crystal display panel, generates auxiliary capacitor driving signals, and includes: first and second voltage trunk lines (VCS1, VCS2) which carry two different voltages, respectively; at least one control signal line (VCTRL1, VCTRL2) carrying one control signal; and a plurality of TFTs (T1, T2, T3, T4) each alternately supplying, to the respective auxiliary capacitor lines (CSn, CSn+1, and the like) in a given cycle, the two different voltages supplied to the auxiliary capacitor line driving circuit (5). Therefore, a liquid crystal display device employing multi-picture element drive method can be provided as a liquid crystal display device that achieves narrowing of a picture frame region as a non-display region and an external circuit board.Type: ApplicationFiled: November 26, 2010Publication date: January 10, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Masahiko Nakamizo, Akihiro Shohraku
-
Publication number: 20120293536Abstract: An object of the present invention is to provide a multi-primary color display device which is capable of handling an increased number of primary colors for color image display with a reduced number of external parts, with reduced increase in the amount of drive circuit and reduced increase in operating speed. An active matrix liquid crystal panel (600) includes a display section (500) constituted by pixel formation portions, each made of four sub pixel-formation portions (Ps) which handle four primary colors. These four sub pixel-formation portions are arranged in a 2×2 matrix pattern. With such a pixel configuration, a source driver (300) drives as many as M source lines (Ls), which is two times the number Mpix of pixels arranged in a horizontal direction. A gate driver (400) is formed on the liquid crystal panel (600) integrally with pixel circuit in the display section (500), and drives as many as N gate lines (Lg), which is two times the number Npix of the pixels arranged in a vertical direction.Type: ApplicationFiled: December 7, 2010Publication date: November 22, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Masashi Yonemaru, Masahiko Nakamizo, Kenichi Ishii
-
Publication number: 20120200482Abstract: A liquid crystal display panel 100 has: a first substrate 11, having an active region AA having pixel electrodes and TFTs, and a gate driver region GDR provided on the outside of the active region AA; and a second substrate 21, disposed opposing the first substrate 11 with a liquid crystal layer 30 interposed therebetween, and having an opposite electrode 23. The opposite electrode 23 opposes the gate driver region GDR with the liquid crystal layer 30 interposed therebetween, and an insulating resin layer 26 is formed on the region of the opposite electrode 23 so that the insulating resin layer 26 opposes the gate driver region GDR. Thus, short-circuit failure between the driver region of the TFT substrate and the opposite electrode is eliminated.Type: ApplicationFiled: September 30, 2010Publication date: August 9, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Tetsuo Fukaya, Yuhichi Saitoh, Hiroyuki Moriwaki, Yasuhiro Nakatake, Yukio kurozumi, Masato Kakuta, Masahiko Nakamizo, Takahiro Umezawa
-
Publication number: 20120146969Abstract: A gate driver is implemented that includes an easily testable shift register to improve panel yields. In a monolithic gate driver including a shift register that operates based on 4-phase clock signals, each stage of the shift register is provided with an inter-stage connecting wiring line for receiving a clock signal other than clock signals received from a clock signal trunk wiring line, from a different stage than the stage; and a contact that connects a wiring line formed on the stage to the inter-stage connecting wiring line. The shift register is grouped every four consecutive stages. Markings formed of different numbers of planar-view circular-shaped structures are formed on bistable circuits of four stages included in each group such that the same type of marking appears every four stages.Type: ApplicationFiled: March 16, 2010Publication date: June 14, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Mayuko Sakamoto, Masashi Yonemaru, Kenichi Ishii, Masahiko Nakamizo
-
Publication number: 20120087459Abstract: To provide a shift register and a display device each capable of satisfactorily preventing noises of individual stage outputs without increasing circuit complexity, each stage of the shift register includes: a first output transistor; a first capacitor; an input gate; a first switching element; a second switching element; a third switching element; a fourth switching element; and a fifth switching element.Type: ApplicationFiled: February 24, 2010Publication date: April 12, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Masahiko Nakamizo, Masashi Yonemaru, Yasuaki Iwase, Kenichi Ishii
-
Publication number: 20120076256Abstract: Disclosed are a shift register and a display device which can suppress noise of output of each stage without causing an increase in circuit scale. Each stage (Xi) of the shift register includes a first output transistor (M5), a second output transistor (M7), a first capacitor (C1), a second capacitor (C2), an input gate (M1), a first switching element (M2), a second switching element (M3), a third switching element (M4), a fourth switching element (M6), and a fifth switching element (M8).Type: ApplicationFiled: February 22, 2010Publication date: March 29, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Masashi Yonemaru, Masahiko Nakamizo
-
Publication number: 20120044133Abstract: Each stage (Xi) of a shift register includes a first output transistor (M5), a first capacitor (C1), an input gate (M1), a first switching element (M2), a second switching element (M3), a third switching element (M4), and a fourth switching element (M6).Type: ApplicationFiled: October 23, 2009Publication date: February 23, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Masahiko Nakamizo, Masashi Yonemaru, Kenichi Ishii, Yasuaki Iwase