Patents by Inventor Masahiko Nakayama

Masahiko Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210129041
    Abstract: The abstract of the disclosure is a thermal-ultrafine bubble generation unit which is configured to generate thermal-ultrafine bubbles by bringing a liquid into film boiling. More specifically, the thermal-ultrafine bubble generation unit in the disclosure includes a temperature detection element that is configured to detect generation of the film boiling.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 6, 2021
    Inventors: Yoshiyuki Imanaka, Takahiro Nakayama, Masahiko Kubota, Akira Yamamoto, Akitoshi Yamada, Yumi Yanai, Hiroyuki Ishinaga, Teruo Ozaki, Toshio Kashino, Hiroki Arai, Kazuki Hirobe, Yukinori Nishikawa, Hisao Okita, Yusuke Komano
  • Publication number: 20210134605
    Abstract: An oxygen concentration is lowered in accordance with a set lowering process, and thereafter a heat treatment is performed. Accordingly, the heat treatment is performed to a substrate W while the oxygen concentration in a heat treating space HS is lowered. Consequently, a treatment atmosphere within the heat treating space is able to be made suitable for a heat treatment process, leading to appropriate film deposition. In addition, the oxygen concentration is lowered in accordance with a concentration level in recipes. This avoids an excessively lowered oxygen concentration, leading to prevention of reduced throughput.
    Type: Application
    Filed: October 24, 2017
    Publication date: May 6, 2021
    Inventors: Chisayo NAKAYAMA, Yuji TANAKA, Masahiko HARUMOTO, Masaya ASAI, Yasuhiro FUKUMOTO, Tomohiro MATSUO, Takeharu ISHII
  • Patent number: 10985210
    Abstract: A nonvolatile storage device includes first and second interconnections and a memory cell between the first and second interconnections. The memory cell includes a storage element, a first switch, and a second switch. The first switch has two terminals and transitions from an off-state to an on-state when a first threshold voltage is applied between its terminals and then voltage between the terminals falls to a first hold voltage. The second switch has two terminals and transitions from an off-state to an on-state when a second threshold voltage is applied between its terminals and then voltage between the terminals falls to a second hold voltage. An off-current of the first switch is less than an off-current of the second switch. The first threshold voltage is greater than the second threshold voltage, which is greater than the first hold voltage, which is greater than or equal to the second hold voltage.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masahiko Nakayama, Toshihiko Nagase, Tomomi Funayama, Hironobu Furuhashi, Kazumasa Sunouchi
  • Patent number: 10985209
    Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masahiko Nakayama, Kazumasa Sunouchi, Gaku Sudo, Tadashi Kai
  • Patent number: 10910032
    Abstract: A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a current level of the second pulse is different from a current level of the first pulse.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya Kishi, Tsuneo Inaba, Daisuke Watanabe, Masahiko Nakayama, Nobuyuki Ogata, Masaru Toko, Hisanori Aikawa, Jyunichi Ozeki, Toshihiko Nagase, Young Min Eeh, Kazuya Sawada
  • Publication number: 20200346594
    Abstract: An instrument panel unit (2) includes an instrument panel (3) and a decorative sheet (4). The instrument panel (3) includes a sticking portion (3a) and an exposed portion (3b). A plurality of insertion grooves 3c and insertion holes 3d are formed alternately at an end on a rear side of the sticking portion (3a), into which bent pieces (4a) formed at a rear end of the decorative sheet (4) are inserted. A groove front-surface (3g) forming the insertion groove (3c) of the instrument panel (3) is formed in a tapered shape such that a width between the groove front-surface and an opposing groove rear-surface (3h) gradually increases upwardly. The bent piece (4a) is formed to be thinner than the groove width at the upper part serving as the entrance part of the insertion groove (3c) and to be thicker than the groove width of a groove bottom-surface (3i).
    Type: Application
    Filed: October 24, 2018
    Publication date: November 5, 2020
    Inventors: Atsushi Yusa, Kenichi Chujo, Yusuke Takamura, Hajime Miyamoto, Toshio Kazami, Satoru Iriyama, Masahiko Nakayama
  • Publication number: 20200303453
    Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 24, 2020
    Inventors: Masahiko NAKAYAMA, Kazumasa SUNOUCHI, Gaku SUDO, Tadashi KAI
  • Publication number: 20200302984
    Abstract: According to one embodiment, a magnetic device includes a stacked body including a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first magnetic layer and the second magnetic layer. The stacked body has a quadrangular planar shape, the stacked body has a first side dimension in a first direction parallel to a surface of a substrate and a thickness in a second direction perpendicular to the surface of the substrate, and a ratio of the first side dimension to the thickness is in a range of 0.10 to 4.0.
    Type: Application
    Filed: August 30, 2019
    Publication date: September 24, 2020
    Inventors: Tadashi KAI, Masahiko NAKAYAMA, Jyunichi OZEKI, Shogo ITAI
  • Publication number: 20200303455
    Abstract: A nonvolatile storage device includes first and second interconnections and a memory cell between the first and second interconnections. The memory cell includes a storage element, a first switch, and a second switch. The first switch has two terminals and transitions from an off-state to an on-state when a first threshold voltage is applied between its terminals and then voltage between the terminals falls to a first hold voltage. The second switch has two terminals and transitions from an off-state to an on-state when a second threshold voltage is applied between its terminals and then voltage between the terminals falls to a second hold voltage. An off-current of the first switch is less than an off-current of the second switch. The first threshold voltage is greater than the second threshold voltage, which is greater than the first hold voltage, which is greater than or equal to the second hold voltage.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 24, 2020
    Inventors: Masahiko NAKAYAMA, Toshihiko NAGASE, Tomomi FUNAYAMA, Hironobu FURUHASHI, Kazumasa SUNOUCHI
  • Publication number: 20200091227
    Abstract: According to one embodiment, a magnetic memory device includes a first memory cell which includes a first stacked structure including a magnetic layer, and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer, wherein each of the first stacked structure and the second stacked structure has a structure in which a plurality of layers including a predetermined layer are stacked, and the predetermined layer included in the first stacked structure and the predetermined layer included in the second stacked structure have different thicknesses.
    Type: Application
    Filed: March 14, 2019
    Publication date: March 19, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masayoshi IWAYAMA, Tatsuya KISHI, Masahiko NAKAYAMA, Toshihiko NAGASE, Daisuke WATANABE, Tadashi KAI
  • Publication number: 20200075671
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, and including a first main surface and a second main surface located opposite to the first main surface, a second magnetic layer provided on a first main surface side of the first magnetic layer, and having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, wherein a saturation magnetization of a part of the first magnetic layer which is located close to the first main surface is higher than a saturation magnetization of a part of the first magnetic layer which is located close to the second main surface.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Jyunichi OZEKI, Masahiko NAKAYAMA, Hiroaki YODA, Eiji KITAGAWA, Takao OCHIAI, Minoru AMANO, Kenji NOMA
  • Patent number: 10446739
    Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. An SAF structure is comprised of the second magnetic layer, the metal layer and the third magnetic layer. A write circuit applies a first voltage and a second voltage having reversed polarity of the first voltage to the resistance change element in a write operation in which the resistance change element is changed from a low-resistance state to a high-resistance state.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: October 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsuneo Inaba, Tatsuya Kishi, Masahiko Nakayama
  • Publication number: 20190259438
    Abstract: A memory device includes a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers. The memory device also includes a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a write current to the magnetoresistive element. A first write current in the first writing includes a first pulse and a second pulse added to the first pulse. A width of the second pulse is smaller than a width of the first pulse, and a scurrent level of the second pulse is different from a current level of the first pulse.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya KISHI, Tsuneo INABA, Daisuke WATANABE, Masahiko NAKAYAMA, Nobuyuki OGATA, Masaru TOKO, Hisanori AIKAWA, Jyunichi OZEKI, Toshihiko NAGASE, Young Min EEH, Kazuya SAWADA
  • Patent number: 10325640
    Abstract: According to one embodiment, a memory device includes: a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers; and a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a current pulse to the magnetoresistive element. A first pulse pattern used in the first writing is different from a second pulse pattern used in the second writing.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: June 18, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya Kishi, Tsuneo Inaba, Daisuke Watanabe, Masahiko Nakayama, Nobuyuki Ogata, Masaru Toko, Hisanori Aikawa, Jyunichi Ozeki, Toshihiko Nagase, Young Min Eeh, Kazuya Sawada
  • Publication number: 20190096461
    Abstract: According to one embodiment, a memory device includes: a first memory element arranged above a substrate; a first contact portion adjacent to the first memory element in a first direction parallel to a surface of the substrate; a second contact portion arranged above the first memory element in a second direction perpendicular to the surface of the substrate; and a second memory element arranged above the first contact portion in the second direction. First dimensions at upper parts of the first and second memory elements are smaller than second dimensions at lower parts of the first and second memory elements, and third dimensions at upper parts of the first and second contact portions are larger than fourth dimensions at lower parts of the first and second contact portions.
    Type: Application
    Filed: March 9, 2018
    Publication date: March 28, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masahiro Koike, Shogo Itai, Tadaomi Daibou, Chikayoshi Kamata, Junichi Ito, Masahiko Nakayama
  • Publication number: 20180277743
    Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A resistance change element has first, second and third magnetic layers and a non-magnetic layer disposed between the first and second magnetic layers, and a metal layer disposed between the second and third magnetic layers. An SAF structure is comprised of the second magnetic layer, the metal layer and the third magnetic layer. A write circuit applies a first voltage and a second voltage having reversed polarity of the first voltage to the resistance change element in a write operation in which the resistance change element is changed from a low-resistance state to a high-resistance state.
    Type: Application
    Filed: September 12, 2017
    Publication date: September 27, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tsuneo INABA, Tatsuya KISHI, Masahiko NAKAYAMA
  • Patent number: 9984736
    Abstract: According to an embodiment, a magnetic storage device includes a first, second, and third magnetoresistive effect elements, and a controller. The second and third magnetoresistive effect elements are in proximity to the first magnetoresistive effect element. When the controller receives an command which is associated with an operation of writing a first data item to the first magnetoresistive effect element, the controller is configured to perform a first operation of writing the first data item to the first magnetoresistive effect element, and a second operation of writing a second data item different from the first data item to the second magnetoresistive effect element and the third magnetoresistive effect element.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: May 29, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ahmetserdar Demiray, Masahiko Nakayama, Hiroshi Watanabe
  • Patent number: 9947380
    Abstract: According to one embodiment, a memory includes a magnetoresistive element, a reference cell, a sense amplifier comparing a first current flowing in the magnetoresistive element with a second current flowing in the reference cell, a first transistor having a first control terminal controlling a value of the first current, a second transistor having a second control terminal controlling a value of the second current, and a controller applying a first potential to the first control terminal and a second potential to the second control terminal in a first operation, and applying the first potential to the first control terminal and a third potential larger than the second potential to the second control terminal in a second operation.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: April 17, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masahiko Nakayama, Masashi Kawamura, Katsuhiko Hoya, Mikio Miyata, Minoru Amano
  • Publication number: 20180075895
    Abstract: According to one embodiment, a memory device includes: a magnetoresistive element including first and second magnetic layers and a non-magnetic layer provided between the first and second magnetic layers; and a write circuit which controls a first writing setting magnetization of the first and second magnetic layers in a parallel state and a second writing setting the magnetization of the first and second magnetic layers in an antiparallel state, and applies a current pulse to the magnetoresistive element. A first pulse pattern used in the first writing is different from a second pulse pattern used in the second writing.
    Type: Application
    Filed: March 10, 2017
    Publication date: March 15, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya KISHI, Tsuneo INABA, Daisuke WATANABE, Masahiko NAKAYAMA, Nobuyuki OGATA, Masaru TOKO, Hisanori AIKAWA, Jyunichi OZEKI, Toshihiko NAGASE, Young Min EEH, Kazuya SAWADA
  • Publication number: 20180053542
    Abstract: According to an embodiment, a magnetic storage device includes a first, second, and third magnetoresistive effect elements, and a controller. The second and third magnetoresistive effect elements are in proximity to the first magnetoresistive effect element. When the controller receives an command which is associated with an operation of writing a first data item to the first magnetoresistive effect element, the controller is configured to perform a first operation of writing the first data item to the first magnetoresistive effect element, and a second operation of writing a second data item different from the first data item to the second magnetoresistive effect element and the third magnetoresistive effect element.
    Type: Application
    Filed: February 6, 2017
    Publication date: February 22, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Ahmetserdar DEMIRAY, Masahiko NAKAYAMA, Hiroshi WATANABE