Patents by Inventor Masahiko Nakayama

Masahiko Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9893121
    Abstract: According to one embodiment, a magnetic memory includes a first metal layer including a first metal, a second metal layer on the first metal layer, the second metal layer including a second metal which is more easily oxidized than the first metal, the second metal layer having a first sidewall portion which contacts the first metal layer, and the second metal layer having a second sidewall portion above the first sidewall portion, the second sidewall portion which steps back from the first sidewall portion, a magnetoresistive element on the second metal layer, a third metal layer on the magnetoresistive element, and a first material which contacts a sidewall portion of the magnetoresistive element and the second sidewall portion of the second metal layer, the first material including an oxide of the second metal.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: February 13, 2018
    Assignees: Toshiba Memory Corporation, SK Hynix, Inc.
    Inventors: Yasuyuki Sonoda, Masahiko Nakayama, Min Suk Lee, Masatoshi Yoshikawa, Kuniaki Sugiura, Ji Hwan Hwang
  • Patent number: 9858973
    Abstract: According to one embodiment, a variable change memory includes a bit line, a word line, a memory cell array, a resonance line, a clock generator, and a write driver. The bit line extends in a first direction. The word line extends in a second direction. The memory cell array includes blocks. The each block includes memory cells including a transistor and a variable resistive element. The resonance line connects to a bit line. The clock generator is arranged in the memory cell array and applies a voltage to the resonance line. The write driver supplies a write current to the bit line. The voltage oscillates at the predetermined period and the write current are supplied to the bit line.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shintaro Sakai, Masahiko Nakayama, Katsuyuki Fujita, Hiromi Noro
  • Publication number: 20170263679
    Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, and including a first main surface and a second main surface located opposite to the first main surface, a second magnetic layer provided on a first main surface side of the first magnetic layer, and having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, wherein saturation magnetization of part of the first magnetic layer which is located close to the first main surface is higher than saturation magnetization of part of the first magnetic layer which is located close to the second main surface.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jyunichi OZEKI, Masahiko NAKAYAMA, Hiroaki YODA, Eiji KITAGAWA, Takao OCHIAI, Minoru AMANO, Kenji NOMA
  • Publication number: 20170263336
    Abstract: According to one embodiment, a memory includes a magnetoresistive element, a reference cell, a sense amplifier comparing a first current flowing in the magnetoresistive element with a second current flowing in the reference cell, a first transistor having a first control terminal controlling a value of the first current, a second transistor having a second control terminal controlling a value of the second current, and a controller applying a first potential to the first control terminal and a second potential to the second control terminal in a first operation, and applying the first potential to the first control terminal and a third potential larger than the second potential to the second control terminal in a second operation.
    Type: Application
    Filed: September 15, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiko NAKAYAMA, Masashi KAWAMURA, Katsuhiko HOYA, Mikio MIYATA, Minoru AMANO
  • Patent number: 9705076
    Abstract: According to one embodiment, there is provided a magnetoresistive element, including a lower electrode having crystallinity on a substrate, a first conductive layer including an amorphous state on the lower electrode, a buffer layer on the first conductive layer, and an MTJ element on the buffer layer.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: July 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Nagamine, Youngmin Eeh, Koji Ueda, Daisuke Watanabe, Kazuya Sawada, Toshihiko Nagase, Masahiko Nakayama
  • Patent number: 9672887
    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell stably storing data after a first time from an end of a write operation, a buffer latching the data in the write operation, and a control circuit controlling a first read operation when the first read operation is executed right after the write operation for the first memory cell is executed, where the first read operation is an operation for the first memory cell, and the first read operation is an operation reading the data from the buffer without accessing the first memory cell.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 6, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hironobu Furuhashi, Masahiko Nakayama, Katsuhiko Hoya
  • Patent number: 9647034
    Abstract: According to one embodiment, a magnetoresistive memory device includes a stacked layer structure includes a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, and a third magnetic layer provided on the first magnetic layer, which is opposite the nonmagnetic layer. The third magnetic layer includes a first magnetic material portion and a second magnetic material portion provided between the stacked layer structure and the first magnetic material portion. The saturation magnetization of the second magnetic material portion is smaller than that of the first magnetic material portion.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 9, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiko Nakayama, Yutaka Hashimoto, Yasuyuki Sonoda, Tadashi Kai, Kenji Noma
  • Publication number: 20170069687
    Abstract: According to one embodiment, a magnetoresistive memory device includes a stacked layer structure includes a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, and a third magnetic layer provided on the first magnetic layer, which is opposite the nonmagnetic layer. The third magnetic layer includes a first magnetic material portion and a second magnetic material portion provided between the stacked layer structure and the first magnetic material portion. The saturation magnetization of the second magnetic material portion is smaller than that of the first magnetic material portion.
    Type: Application
    Filed: March 9, 2016
    Publication date: March 9, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiko NAKAYAMA, Yutaka HASHIMOTO, Yasuyuki SONODA, Tadashi KAI, Kenji NOMA
  • Publication number: 20170069366
    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell stably storing data after a first time from an end of a write operation, a buffer latching the data in the write operation, and a control circuit controlling a first read operation when the first read operation is executed right after the write operation for the first memory cell is executed, where the first read operation is an operation for the first memory cell, and the first read operation is an operation reading the data from the buffer without accessing the first memory cell.
    Type: Application
    Filed: March 10, 2016
    Publication date: March 9, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hironobu FURUHASHI, Masahiko NAKAYAMA, Katsuhiko HOYA
  • Publication number: 20160380028
    Abstract: According to one embodiment, a magnetic memory includes a first metal layer including a first metal, a second metal layer on the first metal layer, the second metal layer including a second metal which is more easily oxidized than the first metal, the second metal layer having a first sidewall portion which contacts the first metal layer, and the second metal layer having a second sidewall portion above the first sidewall portion, the second sidewall portion which steps back from the first sidewall portion, a magnetoresistive element on the second metal layer, a third metal layer on the magnetoresistive element, and a first material which contacts a sidewall portion of the magnetoresistive element and the second sidewall portion of the second metal layer, the first material including an oxide of the second metal.
    Type: Application
    Filed: September 6, 2016
    Publication date: December 29, 2016
    Applicants: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.
    Inventors: Yasuyuki SONODA, Masahiko NAKAYAMA, Min Suk LEE, Masatoshi YOSHIKAWA, Kuniaki SUGIURA, Ji Hwan HWANG
  • Publication number: 20160379697
    Abstract: According to one embodiment, a variable change memory includes a bit line, a word line, a memory cell array, a resonance line, a clock generator, and a write driver. The bit line extends in a first direction. The word line extends in a second direction. The memory cell array includes blocks. The each block includes memory cells including a transistor and a variable resistive element. The resonance line connects to a bit line. The clock generator is arranged in the memory cell array and applies a voltage to the resonance line. The write driver supplies a write current to the bit line. The voltage oscillates at the predetermined period and the write current are supplied to the bit line.
    Type: Application
    Filed: September 9, 2016
    Publication date: December 29, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shintaro SAKAI, Masahiko NAKAYAMA, Katsuyuki FUJITA, Hiromi NORO
  • Patent number: 9466350
    Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect, a magnetoresistive effect element having first and second terminals, the first terminal being electrically connected to the first interconnect, a diode having first and second terminals, the first terminal being electrically connected to the first terminal of the magnetoresistive effect element, the second terminal being electrically connected to the second terminal of the magnetoresistive effect element, and a transistor having source and drain terminals, one of the source and drain terminals being electrically connected to the second terminal of the magnetoresistive effect element and the second terminal of the diode, the other of the source and drain terminals being electrically connected to the second interconnect.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: October 11, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akiyuki Murayama, Eiji Kitagawa, Masahiko Nakayama, Minoru Amano, Takao Ochiai
  • Publication number: 20160267960
    Abstract: According to one embodiment, a magnetic memory device includes a first interconnect, a second interconnect, a magnetoresistive effect element having first and second terminals, the first terminal being electrically connected to the first interconnect, a diode having first and second terminals, the first terminal being electrically connected to the first terminal of the magnetoresistive effect element, the second terminal being electrically connected to the second terminal of the magnetoresistive effect element, and a transistor having source and drain terminals, one of the source and drain terminals being electrically connected to the second terminal of the magnetoresistive effect element and the second terminal of the diode, the other of the source and drain terminals being electrically connected to the second interconnect.
    Type: Application
    Filed: September 8, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akiyuki MURAYAMA, Eiji KITAGAWA, Masahiko NAKAYAMA, Minoru AMANO, Takao OCHIAI
  • Patent number: 9406871
    Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 2, 2016
    Assignees: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.
    Inventors: Masahiko Nakayama, Masatoshi Yoshikawa, Tadashi Kai, Yutaka Hashimoto, Masaru Toko, Hiroaki Yoda, Jae Geun Oh, Keum Bum Lee, Choon Kun Ryu, Hyung Suk Lee, Sook Joo Kim
  • Patent number: 9385304
    Abstract: According to one embodiment, a magnetic memory is disclosed. The memory includes a conductive layer containing a first metal material, a stacked body above the conductive layer, and including a first magnetization film containing a second metal material, a second magnetization film, and a tunnel barrier layer between the first magnetization film and the second magnetization film, and an insulating layer on a side face of the stacked body, and containing an oxide of the first metal material. The first magnetization film and/or the second magnetization film includes a first region positioned in a central portion, and a second region positioned in an edge portion and containing As, P, Ge, Ga, Sb, In, N, Ar, He, F, Cl, Br, I, Si, B, C, O, Zr, Tb, S, Se, or Ti.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: July 5, 2016
    Assignees: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.
    Inventors: Masahiko Nakayama, Tadashi Kai, Masaru Toko, Hiroaki Yoda, Hyung Suk Lee, Jae Geun Oh, Choon Kun Ryu, Min Suk Lee
  • Patent number: 9368717
    Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer. The reference layer includes a first region, and a second region provided outside the first region to surround the same. The second region contains an element contained in the first region and another element being different from the element. The magnetoresistive element further includes a storage layer, and a tunnel barrier layer provided between the reference layer and the storage layer. The storage layer is free from the another element.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: June 14, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaru Toko, Masahiko Nakayama, Kuniaki Sugiura, Yutaka Hashimoto, Tadashi Kai, Akiyuki Murayama, Tatsuya Kishi
  • Patent number: 9299410
    Abstract: According to one embodiment, a magnetic memory includes a cell array includes a plurality of memory cells, each memory cell including a magnetoresistive effect element; and a read circuit to read data from a memory cell selected based on an address signal from among the memory cells. The read circuit selects one determination level from among a plurality of determination levels corresponding to a position of a magnetoresistive effect element in the cell array and uses the selected determination level to perform reading of the data.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: March 29, 2016
    Inventors: Shintaro Sakai, Masahiko Nakayama
  • Patent number: 9269890
    Abstract: According to one embodiment, a magnetoresistance effect element includes a reference layer, a shift canceling layer, a storage layer provided between the reference layer and the shift canceling layer, a tunnel barrier layer provided between the reference layer and the storage layer, and a spacer layer provided between the shift canceling layer and the storage layer, wherein a pattern of the storage layer is provided inside a pattern of the shift canceling layer when the patterns of the storage layer and the shift canceling layer are viewed from a direction perpendicular to the patterns of the storage layer and the shift canceling layer.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: February 23, 2016
    Inventors: Masahiko Nakayama, Toshihiko Nagase, Tadashi Kai, Youngmin Eeh, Koji Ueda, Yutaka Hashimoto, Daisuke Watanabe, Kazuya Sawada
  • Patent number: 9236563
    Abstract: According to one embodiment, a magnetic memory device includes a magnetoresistance effect element having a structure in which a first magnetic layer, a nonmagnetic layer, a second magnetic layer, and a third magnetic layer are stacked, wherein the third magnetic layer comprises a first region and a plurality of second regions, and each of the second regions is surrounded by the first region, has conductivity, and has a greater magnetic property than the first region.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: January 12, 2016
    Inventors: Yutaka Hashimoto, Tadashi Kai, Masahiko Nakayama, Hiroaki Yoda, Toshihiko Nagase, Masatoshi Yoshikawa, Yasuyuki Sonoda
  • Patent number: 9196822
    Abstract: A magnetoresistive effect element in one or more embodiments of the present invention is provided with a memory layer with a variable magnetization direction having a magnetic anisotropy in a direction perpendicular to a film surface, a reference layer with an invariable magnetization direction having the magnetic anisotropy in a direction perpendicular to the film surface, and a tunnel barrier layer formed between the memory layer and the reference layer. The tunnel barrier layer has a first portion at the central part in the film surface and a second portion at a peripheral part. The second portion contains at least boron and oxygen.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: November 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeto Fukatsu, Tatsuya Kishi, Masahiko Nakayama, Akiyuki Murayama