Abstract: A method for forming a cylindrical capacitor having a metal-nitride bottom electrode, capacitor insulation film and a top electrode in a DRAM device includes the step of forming a photoresist film on the bottom electrode in a cylindrical hole, removing the photoresist film by using a plasma ashing treatment using non-oxygen gas, and consecutively forming the insulation film and the top electrode on the bottom electrode. The plasma ashing treatment uses a bias power for accelerating the plasma gas into the cylindrical trench.

Abstract: When the occurrence of the bowing is controlled through the etching conditions, a change in etching conditions causes the bowing. Another problem is a requirement of the larger-sized apparatus for the substrate with a larger diameter in order to allow a whole substrate being subjected equally to the conditions under which no bowing occurs. In the present invention, a first etching is stopped at a depth where no bowing occurs to form an opening section. Next, a protective film for etching is formed on a region of the wall surface of the hole in the opening section where a bowing is liable to appear when an opening is formed further. After that, a second etching is carried out to form an opening further, and thereby a minute opening with an aspect ratio of 13 or higher is made, while suppressing the occurrence of the bowing well.

Abstract: A semiconductor device according to the present invention includes a cylindrical capacitor. An amorphous silicon layer serving as a lower electrode of the cylindrical capacitor has a two-layer structure including a lower high-concentration impurity sublayer and an upper low-concentration impurity sublayer. The blockage of a cylinder is prevented by etching the upper low-concentration impurity sublayer in a lower region of the cylinder and thereby reducing the crystal grain size of hemispherical silicon grains formed in the lower region.

Abstract: A method of manufacturing a semiconductor device having a dual-gate structure includes the steps of forming P-type and N-type gate silicon layers in different regions; implanting P-type or N-type impurities into the P-type and N-type gate silicon layers; depositing a metallic film on the P-type and N-type gate silicon layers; patterning the metallic film by using a mask having a gate-electrodes pattern, patterning the P-type and N-type gate silicon layers by the mask and the patterned metallic film to leave P-type and N-type gate silicon electrodes.

Abstract: When the occurrence of the bowing is controlled through the etching conditions, a change in etching conditions causes the bowing. Another problem is a requirement of the larger-sized apparatus for the substrate with a larger diameter in order to allow a whole substrate being subjected equally to the conditions under which no bowing occurs.

Abstract: The method of manufacturing a semiconductor device according to the present invention has a step of forming a first layer-insulating film to be adhered to a diffused layer formed on the surface of a semiconductor substrate or to a lower wiring formed on the semiconductor substrate, using a first dielectric, a step of disposing mutually parallel upper wirings on the first layer-insulating film and forming a protective film composed of a second dielectric having an etching rate smaller than that of the first dielectric on the top face and side faces of the upper wirings, and a step of forming a contact hole penetrating the first layer-insulating film and reaching the diffused layer or the lower wiring by a dry etching that uses the protective insulating film as a part of an etching mask.

Abstract: The method of manufacturing a semiconductor device according to the present invention has a step of forming a first layer-insulating film to be adhered to a diffused layer formed on the surface of a semiconductor substrate or to a lower wiring formed on the semiconductor substrate, using a first dielectric, a step of disposing mutually parallel upper wirings on the first layer-insulating film and forming a protective film composed of a second dielectric having an etching rate smaller than that of the first dielectric on the top face and side faces of the upper wirings, and a step of forming a contact hole penetrating the first layer-insulating film and reaching the diffused layer or the lower wiring by a dry etching that uses the protective insulating film as a part of an etching mask.

Abstract: A TiN film and an ARL-SiON film (plasma SiO2 film+plasma SiON film) are deposited on a metal interconnection layer. The film thickness and the film quality of the ARL-SiON film is optmized to minimize the reflectance factor of the metal interconnection layer, and the composition of the ARL-SiON film is so adjusted that the ARL-SiON film can be easily dissolved by a hydrofluoric acid in a later process. The multi-layer antireflection layer composed of the TiN film and the ARL-SiON film, and the underlying metal interconnection layer are continuously dry-etched in the same processing chamber. At this time, the basis of the etching gas is composed of a combination of chlorine based gases (Cl containing gas such as Cl2, BCl3, HCl) which is the same as that used for etching the metal film. Furthermore, when the etching gas composed of a combination of Cl2 and BCl3 is used, the mixing ratio of the etching gas is changed.

Abstract: The present invention provides an etching apparatus and a method of preventing electrical damage of the device due to the charge-up and preventing a wiring short due to etching residues when forming wiring on the device formed in a semiconductor substrate. In a wiring etching method in a semiconductor substrate, including a step of a conductor in a semiconductor device by plasma etching, the etching of the above conductor under a Continuous Wave condition (a condition where a plasma discharge occurs continuously) is performed to a predetermined film thickness before the entire conductor is etched, and after that the etching is performed under a Time Modulation condition (a condition where a plasma discharge occurs intermittently) thereafter.

Abstract: An aluminum-copper alloy layer is patterned through a photo-lithography followed by a dry etching, and side walls of etching residue containing aluminum chloride, which is causative of after-corrosion in the aluminum-copper alloy line, is grown during the dry etching, wherein the side walls are exposed to gaseous mixture containing ionic water vapor so that hydrogen ion and/or the hydroxyl group reacts with the aluminum chloride, thereby converting the aluminum chloride to aluminum and/or aluminum hydroxide and hydrochloric acid vaporized into vacuum.