Abstract: A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.

Abstract: A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.

Abstract: A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.

Abstract: A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.

Abstract: A sidewall core that is slimmed is formed in a memory cell array area by patterning a polysilicon layer formed over a silicon nitride layer. A silicon oxide layer that at least covers side surfaces of the sidewall core and the polysilicon layer are sequentially formed and an embedded hard mask is formed by etching back the polysilicon layer. Thereafter, the silicon nitride layer within the memory cell array area that does not overlap with the sidewall core or the embedded hard mask and the silicon nitride layer within a peripheral circuit area that overlaps with a positioning monitor mark are exposed by etching the silicon oxide layer, and then the silicon nitride layer that is to be etched is patterned.

Abstract: A manufacturing method for a semiconductor device includes: forming a first layer on a member to be etched; forming a first hard mask that includes a first hard mask pattern, in the first layer; forming a second layer on the first hard mask and on an exposed surface of the member to be etched; removing by selective etching the second layer to form a side wall core that includes a core pattern; forming side wall spacers on side walls of the side wall core; and using the side wall spacers and the first hard mask to remove by etching the member to be etched.

Abstract: A method for fabricating a semiconductor device includes the following processes. A first groove is formed in a first insulating film. A first conductive film is formed on inner surfaces of the first groove. A second groove is formed in the first insulating film to remove a part of the first conductive film. The second groove intersects the first groove.

Abstract: A semiconductor device includes a shallow isolation trench (STI) structure on a silicon substrate for isolating element-forming regions from one another. The surface region of the silicon substrate in the element-forming regions, as viewed in the extending direction of the gate electrode lines, once falls and thereafter rises monotonically from the periphery toward the center of the element-forming regions.

Abstract: A sidewall core that is slimmed is formed in a memory cell array area by patterning a polysilicon layer formed over a silicon nitride layer. A silicon oxide layer that at least covers side surfaces of the sidewall core and the polysilicon layer are sequentially formed and an embedded hard mask is formed by etching back the polysilicon layer. Thereafter, the silicon nitride layer within the memory cell array area that does not overlap with the sidewall core or the embedded hard mask and the silicon nitride layer within a peripheral circuit area that overlaps with a positioning monitor mark are exposed by etching the silicon oxide layer, and then the silicon nitride layer that is to be etched is patterned.

Abstract: A semiconductor device manufacturing method may include the following processes. A semiconductor substrate is partially removed using a first insulating film having first and second portions as a mask to form first and second pillars of the semiconductor substrate. A second insulating film is formed on side surfaces of the first and second pillars. A silicon film is formed on the first and second insulating films. A first part of the silicon film, which is on upper surfaces of the first and second portions, is removed. A coating film, which covers the upper surfaces of the first and second portions, is formed over the semiconductor substrate. The coating film is partially removed to expose the first insulating film and a second part of the silicon film. The second part is on side surfaces of the first and second portions. The second part is removed by dry etching.

Abstract: A semiconductor device manufacturing method may include the following processes. A semiconductor substrate is partially removed using a first insulating film having first and second portions as a mask to form first and second pillars of the semiconductor substrate. A second insulating film is formed on side surfaces of the first and second pillars. A silicon film is formed on the first and second insulating films. A first part of the silicon film, which is on upper surfaces of the first and second portions, is removed. A coating film, which covers the upper surfaces of the first and second portions, is formed over the semiconductor substrate. The coating film is partially removed to expose the first insulating film and a second part of the silicon film. The second part is on side surfaces of the first and second portions. The second part is removed by dry etching.

Abstract: A semiconductor memory device includes diffusion regions formed in an active region; cell contacts connected to the diffusion regions, respectively; pillars connected to the cell contacts, respectively; a bit line connected to the pillar; capacitor contacts connected to the pillars, respectively; and storage capacitors connected to the capacitor contacts, respectively. Accordingly, the pillars exist between the cell contacts and the capacitor contacts, and thus, depths of the capacitor contacts are made correspondingly shorter. Therefore, it becomes possible to prevent occurrence of shorting defects while decreasing resistance values of the capacitor contacts.

Abstract: A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain regions. A second inter-layer insulator over the first inter-layer insulator and the cell contact plugs has second contact holes that reach the cell contact plugs. Contact plugs each have first and second portions. The first portion is in the second contact hole. The second portion extends over the first second inter-layer insulator. Metal barrier layers cover the upper surfaces of the second portions of the contact plugs. Capacitors each have a bottom electrode layer, a capacitive insulating layer and a top electrode layer. The bottom electrode layers each have a contact portion that contacts with the metal barrier layer.

Abstract: A method of forming a semiconductor device includes the following processes. First grooves are formed in a first insulating layer. A conductive material is formed which fills in each of the first grooves. A first mask is formed over the first insulating layer and the conductive material. The first mask has openings that define second grooves crossing the first grooves in plan view. The second grooves are formed in the first insulating layer and the conductive material by using the first mask. A plurality of conductive pillars are formed by removing a part of the conductive material in each of the first grooves.

Abstract: A manufacturing method for a semiconductor device includes: forming a first layer on a member to be etched; forming a first hard mask that includes a first hard mask pattern, in the first layer; forming a second layer on the first hard mask and on an exposed surface of the member to be etched; removing by selective etching the second layer to form a side wall core that includes a core pattern; forming side wall spacers on side walls of the side wall core; and using the side wall spacers and the first hard mask to remove by etching the member to be etched.

Abstract: A semiconductor memory device includes diffusion regions formed in an active region; cell contacts connected to the diffusion regions, respectively; pillars connected to the cell contacts, respectively; a bit line connected to the pillar; capacitor contacts connected to the pillars, respectively; and storage capacitors connected to the capacitor contacts, respectively. Accordingly, the pillars exist between the cell contacts and the capacitor contacts, and thus, depths of the capacitor contacts are made correspondingly shorter. Therefore, it becomes possible to prevent occurrence of shorting defects while decreasing resistance values of the capacitor contacts.

Abstract: A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain regions. A second inter-layer insulator over the first inter-layer insulator and the cell contact plugs has second contact holes that reach the cell contact plugs. Contact plugs each have first and second portions. The first portion is in the second contact hole. The second portion extends over the first second inter-layer insulator. Metal barrier layers cover the upper surfaces of the second portions of the contact plugs. Capacitors each have a bottom electrode layer, a capacitive insulating layer and a top electrode layer. The bottom electrode layers each have a contact portion that contacts with the metal barrier layer.

Abstract: A semiconductor device includes a shallow isolation trench (STI) structure on a silicon substrate for isolating element-forming regions from one another. The surface region of the silicon substrate in the element-forming regions, as viewed in the extending direction of the gate electrode lines, once falls and thereafter rises monotonically from the periphery toward the center of the element-forming regions.

Abstract: A method of fabricating a semiconductor device includes: forming element isolation parts that enclose a plurality of active regions in which transistors are formed and that have profiles perpendicular to the substrate surface that are reverse tapered shapes; after forming the element isolation parts, forming an oxidation-resistant insulation mask that covers the regions of the sources and drains of the transistors in the plurality of active regions; subjecting the substrate to anisotropic etching from above the oxidation-resistant insulation mask; forming trenches for trench gates in the active regions; removing the natural oxidation film that has formed on the substrate surface of the trenches; thereafter heating in a hydrogen atmosphere; after the heat treatment, removing the oxidation-resistant insulation mask; after removing the oxidation-resistant insulation mask, cleaning with an ammonium-hydrogen peroxide mixture; and after cleaning, forming a gate oxide film on the substrate surface of the trenches by

Abstract: A semiconductor device according to the present invention includes a cylindrical capacitor. An amorphous silicon layer serving as a lower electrode of the cylindrical capacitor has a two-layer structure including a lower high-concentration impurity sublayer and an upper low-concentration impurity sublayer. The blockage of a cylinder is prevented by etching the upper low-concentration impurity sublayer in a lower region of the cylinder and thereby reducing the crystal grain size of hemispherical silicon grains formed in the lower region.