Patents by Inventor Masahiko Onishi
Masahiko Onishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150222469Abstract: A compensation apparatus compensates a quadrature-demodulated signal output from a quadrature demodulator 5 that performs quadrature demodulation by using a signal of a carrier frequency fc, by removing an image component caused by the quadrature demodulator 5 from the quadrature-demodulated signal. The compensation apparatus includes a signal generator 10 that generates a reference signal having a predetermined bandwidth in a reception band, and provides the reference signal to an input side of the quadrature demodulator 5. The reference signal includes a frequency band that is biased to either a higher-frequency side or a lower-frequency side with respect to the carrier frequency.Type: ApplicationFiled: April 17, 2015Publication date: August 6, 2015Inventors: Masahiko ONISHI, Isao KATSURA
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Publication number: 20150129924Abstract: In a method for producing a semiconductor light emitting device: a semiconductor lamination of first and second semiconductor layers having different conductive types is formed; a portion of the semiconductor lamination is removed to expose an area of a surface of the first semiconductor layer; a conductor layer connecting the first and second semiconductor layers is formed; a first electrode is formed on the exposed areas of the first semiconductor layer and a second electrode is formed on an upper surface of the second semiconductor layer; a barrier layer covering at least one of the first and second electrodes is formed; and a connection part in the conductor layer connecting the first and second semiconductor layers is removed.Type: ApplicationFiled: January 23, 2015Publication date: May 14, 2015Inventors: Masahiko ONISHI, Shun KITAHAMA
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Patent number: 9000469Abstract: A nitride group semiconductor light emitting device includes a nitride group semiconductor layer, and an electrode structure. The electrode structure is arranged on or above the semiconductor layer, and includes a plurality of deposited metal layers. The plurality of deposited metal layers of the electrode structure includes first and second metal layers. The first metal layer is arranged on the semiconductor layer side. The second metal layer is arranged on or above the first metal layer. The first metal layer contains Cr, and a first metal material. The first metal material has a reflectivity higher than Cr at the light emission peak wavelength of the light emitting device. According to this construction, the first metal layer can have a higher reflectivity as compared with the case where the first metal layer is only formed of Cr, but can keep tight contact with the semiconductor layer.Type: GrantFiled: October 13, 2011Date of Patent: April 7, 2015Assignee: Nichia CorporationInventors: Yasuhiro Miki, Masahiko Onishi, Hirofumi Nishiyama, Shusaku Bando
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Patent number: 8969898Abstract: In a method for producing a semiconductor light emitting device: a semiconductor lamination of first and second semiconductor layers having different conductive types is formed; a portion of the semiconductor lamination is removed to expose an area of a surface of the first semiconductor layer; a conductor layer connecting the first and second semiconductor layers is formed; a first electrode is formed on the exposed areas of the first semiconductor layer and a second electrode is formed on an upper surface of the second semiconductor layer; a barrier layer covering at least one of the first and second electrodes is formed; and a connection part in the conductor layer connecting the first and second semiconductor layers is removed.Type: GrantFiled: February 21, 2013Date of Patent: March 3, 2015Assignee: Nichia CorporationInventors: Masahiko Onishi, Shun Kitahama
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Patent number: 8913690Abstract: A quadrature modulation error is compensated without providing an additional feedback loop for detecting quadrature modulation error. An amplifier circuit includes: a quadrature modulator; an amplifier that amplifies a quadrature-modulated signal; a distortion compensation section that compensates distortion to be caused in the amplifier based on first compensation coefficients; a quadrature modulation error compensation section that compensates for a quadrature modulation error; an updating section that updates second compensation coefficients for compensating the quadrature modulation error; an error estimation section that estimates an error of the quadrature modulation error; and a prediction section that calculates a prediction value of an output of the amplifier after updating of the second compensation coefficients. The second compensation coefficients are updated based on the estimated error. The prediction value is calculated based on the estimated error and the amplifier output.Type: GrantFiled: February 6, 2012Date of Patent: December 16, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventor: Masahiko Onishi
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Patent number: 8854128Abstract: Signal timing adjustment in an amplifying device is appropriately performed by phase adjustment by a digital filter. The amplifying device includes an amplifier; an amplitude-voltage converting unit 12 that performs a desired process on a signal relating to operation of the amplifier, whereby the signal is band-broadened; and a timing adjusting unit 15a that performs timing adjustment of the signal to be provided to the amplifier, by phase adjustment by a digital filter. The timing adjusting unit 15a performs the timing adjustment of the signal at a stage before the signal is band-broadened by the amplitude-voltage converting unit 12.Type: GrantFiled: November 10, 2010Date of Patent: October 7, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventor: Masahiko Onishi
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Publication number: 20140140444Abstract: A compensation apparatus compensates a quadrature-demodulated signal output from a quadrature demodulator 5 that performs quadrature demodulation by using a signal of a carrier frequency fc, by removing an image component caused by the quadrature demodulator 5 from the quadrature-demodulated signal. The compensation apparatus includes a signal generator 10 that generates a reference signal having a predetermined bandwidth in a reception band, and provides the reference signal to an input side of the quadrature demodulator 5. The reference signal includes a frequency band that is biased to either a higher-frequency side or a lower-frequency side with respect to the carrier frequency.Type: ApplicationFiled: July 24, 2012Publication date: May 22, 2014Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Masahiko Onishi, Isao Katsura
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Publication number: 20140064406Abstract: A quadrature modulation error is compensated without providing an additional feedback loop for detecting quadrature modulation error. An amplifier circuit includes: a quadrature modulator; an amplifier that amplifies a quadrature-modulated signal; a distortion compensation section that compensates distortion to be caused in the amplifier based on first compensation coefficients; a quadrature modulation error compensation section that compensates for a quadrature modulation error; an updating section that updates second compensation coefficients for compensating the quadrature modulation error; an error estimation section that estimates an error of the quadrature modulation error; and a prediction section that calculates a prediction value of an output of the amplifier after updating of the second compensation coefficients. The second compensation coefficients are updated based on the estimated error. The prediction value is calculated based on the estimated error and the amplifier output.Type: ApplicationFiled: February 6, 2012Publication date: March 6, 2014Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Masahiko Onishi
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Patent number: 8665017Abstract: An amplifier circuit of envelope tracking scheme has a timing adjusting unit having a finite number of adjustment values for adjusting time by which the output is delayed from the input, and capable of adjusting a time difference between an input signal and a power supply voltage which reach an amplifier, by making a selection from the adjustment values; a test signal output unit capable of repeatedly sending out a test signal serving as the input signal at predetermined cycles; and an adjustment value determining unit sequentially measuring output power for m (?k) periods from the amplifier while changing an adjustment value of the timing adjusting unit to a different value every k periods of the test signal, searching for an adjustment value at which a total sum of the output power form periods is maximum, and setting the adjustment value on the timing adjusting unit.Type: GrantFiled: December 13, 2010Date of Patent: March 4, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventor: Masahiko Onishi
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Patent number: 8658441Abstract: To provide a method of manufacturing a nitride semiconductor light emitting element, which has a small number of steps and thus, can improve productivity, the method of manufacturing a nitride semiconductor light emitting element including a nitride semiconductor light emitting element structure having an n-type nitride semiconductor layer and a p-side nitride semiconductor layer which are laminated on a substrate, an n-side pad electrode connecting surface and a p-side pad electrode connecting surface which are formed on the same plane of the substrate; a n-side pad electrode on the n-side pad electrode connecting surface; and a p-side pad electrode on the p-side pad electrode connecting surface, and in the manufacturing method, a pad electrode layer forming step, a resist pattern forming step, a pad electrode layer etching step, a protective layer forming step and a resist pattern removing step are sequentially performed.Type: GrantFiled: May 18, 2012Date of Patent: February 25, 2014Assignee: Nichia CorporationInventors: Shusaku Bando, Yasuhiro Miki, Masahiko Onishi, Hirofumi Nishiyama
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Publication number: 20130285743Abstract: Distortion compensation is performed taking into account a memory effect that occurs in a signal path other than an input-to-output path of an amplifier. An amplifier circuit 1 includes an amplifier 2 that amplifies a signal, a variable power supply 3 that varies a power supply voltage of the amplifier 2 in accordance with envelope change, and a distortion compensation section 4 that performs compensation for distortion characteristics. The distortion compensation section 4 performs the distortion compensation, based on an amplifier model which represents a memory effect that occurs on a path from a signal input port 2a of the amplifier 2 to a signal output port 2b thereof, and a memory effect that occurs on a path from a power supply port 2c of the amplifier 2 to the signal output port 2b thereof.Type: ApplicationFiled: November 30, 2011Publication date: October 31, 2013Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Masahiko Onishi
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Publication number: 20130256732Abstract: A nitride group semiconductor light emitting device includes a nitride group semiconductor layer, and an electrode structure. The electrode structure is arranged on or above the semiconductor layer, and includes a plurality of deposited metal layers. The plurality of deposited metal layers of the electrode structure includes first and second and metal layers. The first metal layer is arranged on the semiconductor layer side. The second metal layer is arranged on or above the first metal layer. The first metal layer contains Cr, and a first metal material. The first metal material has a reflectivity higher than Cr at the light emission peak wavelength of the light emitting device. According to this construction, the first metal layer can have a higher reflectivity as compared with the case where the first metal layer is only formed of Cr, but can keep tight contact with the semiconductor layer.Type: ApplicationFiled: October 13, 2011Publication date: October 3, 2013Applicant: NICHIA CORPORATIONInventors: Yasuhiro Miki, Masahiko Onishi, Hirofumi Nishiyama, Shusaku Bando
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Patent number: 8471632Abstract: Disclosed is a distortion compensation circuit that efficiently compensates for distortion. A distortion compensation circuit (20) comprises a sampling memory unit (21), which accumulates an input signal and an output signal from an amplifier (4), a model estimation unit (22), which reads the input and output signals that are accumulated upon the sampling memory unit (21), estimates a model that represents an input/output characteristic of the amplifier (4), and outputs a coefficient that denotes the model thus estimated, and a distortion compensation unit (23), which compensates for a distortion of the amplifier (4), based on the coefficient.Type: GrantFiled: September 30, 2009Date of Patent: June 25, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Masahiko Onishi, Mikhail Illarionov
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Patent number: 8390377Abstract: A distortion compensation circuit capable of realizing highly accurate distortion compensation by updating a model even under a situation in which the appearance frequency of an input signal having a maximum value is low. A DPD processor 2 includes an inverse model estimation unit 22, which estimates an inverse model for a model expressing input-output characteristics of an HPA 6 based on an input signal S1 to the HPA 6 and an output signal S10 from the HPA 6, a distortion compensation unit 26, which compensates for distortion of the input-output characteristics by adding the inverse model to the input signal S1, and a sampling circuit 20, which samples the signals S2 and S10 in a predetermined time immediately before the sampling and inputs the signals S2 and S10 to the inverse model estimation unit 22.Type: GrantFiled: October 19, 2009Date of Patent: March 5, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventor: Masahiko Onishi
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Publication number: 20120326777Abstract: An amplifier circuit of envelope tracking has a timing adjusting unit having a finite number of adjustment values for adjusting time by which the output is delayed from the input, and capable of adjusting a time difference between an input signal and a power supply voltage which reach an amplifier, by making a selection from the adjustment values; a test signal output unit capable of repeatedly sending out a test signal serving as the input signal at predetermined cycles; and an adjustment value determining unit sequentially measuring output power for m (?k) periods from the amplifier while changing an adjustment value of the timing adjusting unit to a different value every k period of the test signal, searching for an adjustment value at which a total sum of the output power for m periods is maximum, and setting the adjustment value on the timing adjusting unit.Type: ApplicationFiled: December 13, 2010Publication date: December 27, 2012Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Masahiko Onishi
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Publication number: 20120295373Abstract: To provide a method of manufacturing a nitride semiconductor light emitting element, which has a small number of steps and thus, can improve productivity, the method of manufacturing a nitride semiconductor light emitting element including a nitride semiconductor light emitting element structure having an n-type nitride semiconductor layer and a p-side nitride semiconductor layer which are laminated on a substrate, an n-side pad electrode connecting surface and a p-side pad electrode connecting surface which are formed on the same plane of the substrate; a n-side pad electrode on the n-side pad electrode connecting surface; and a p-side pad electrode on the p-side pad electrode connecting surface, and in the manufacturing method, a pad electrode layer forming step, a resist pattern forming step, a pad electrode layer etching step, a protective layer forming step and a resist pattern removing step are sequentially performed.Type: ApplicationFiled: May 18, 2012Publication date: November 22, 2012Inventors: Shusaku BANDO, Yasuhiro MIKI, Masahiko ONISHI, Hirofumi NISHIYAMA
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Publication number: 20120256688Abstract: Signal timing adjustment in an amplifying device is appropriately performed by phase adjustment by a digital filter. The amplifying device includes an amplifier; an amplitude-voltage converting unit 12 that performs a desired process on a signal relating to operation of the amplifier, whereby the signal is band-broadened; and a timing adjusting unit 15a that performs timing adjustment of the signal to be provided to the amplifier, by phase adjustment by a digital filter. The timing adjusting unit 15a performs the timing adjustment of the signal at a stage before the signal is band-broadened by the amplitude-voltage converting unit 12.Type: ApplicationFiled: November 10, 2010Publication date: October 11, 2012Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Masahiko Onishi
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Publication number: 20110254623Abstract: Disclosed is a distortion compensation circuit that efficiently compensates for distortion. A distortion compensation circuit (20) comprises a sampling memory unit (21), which accumulates an input signal and an output signal from an amplifier (4), a model estimation unit (22), which reads the input and output signals that are accumulated upon the sampling memory unit (21), estimates a model that represents an input/output characteristic of the amplifier (4), and outputs a coefficient that denotes the model thus estimated, and a distortion compensation unit (23), which compensates for a distortion of the amplifier (4), based on the coefficient.Type: ApplicationFiled: September 30, 2009Publication date: October 20, 2011Inventors: Masahiko Onishi, Mikhail Illarionov
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Publication number: 20110254624Abstract: A distortion compensation circuit capable of realizing highly accurate distortion compensation by updating a model even under a situation in which the appearance frequency of an input signal having a maximum value is low. A DPD processor 2 includes an inverse model estimation unit 22, which estimates an inverse model for a model expressing input-output characteristics of an HPA 6 based on an input signal S1 to the HPA 6 and an output signal S10 from the HPA 6, a distortion compensation unit 26, which compensates for distortion of the input-output characteristics by adding the inverse model to the input signal S1, and a sampling circuit 20, which samples the signals S2 and S10 in a predetermined time immediately before the sampling and inputs the signals S2 and S10 to the inverse model estimation unit 22.Type: ApplicationFiled: October 19, 2009Publication date: October 20, 2011Inventor: Masahiko Onishi
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Patent number: 7947996Abstract: It is an important factor in application to the illumination field and the like to obtain a characteristic excellent in power efficiency in a light emitting element. The present invention provides a semiconductor light emitting element including: first and second conductive type semiconductor layers; first and second electrodes respectively provided on the same plane sides as the first and second conductive type semiconductor layers; and a light emitting structure, provided with the second electrode and including the first and second conductive type semiconductor layers, wherein the first electrode provided on an exposed surface of the first conductive type semiconductor layer at least has a translucent first layer and a reflective second layer, and the first layer has projecting portions projected from both sides of the second layer in a cross section of the element crossing over the light emitting structure and the first electrode.Type: GrantFiled: June 27, 2007Date of Patent: May 24, 2011Assignee: Nichia CorporationInventors: Takahiko Sakamoto, Masahiko Onishi, Yoshiki Inoue