Patents by Inventor Masahiko Onishi

Masahiko Onishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120256688
    Abstract: Signal timing adjustment in an amplifying device is appropriately performed by phase adjustment by a digital filter. The amplifying device includes an amplifier; an amplitude-voltage converting unit 12 that performs a desired process on a signal relating to operation of the amplifier, whereby the signal is band-broadened; and a timing adjusting unit 15a that performs timing adjustment of the signal to be provided to the amplifier, by phase adjustment by a digital filter. The timing adjusting unit 15a performs the timing adjustment of the signal at a stage before the signal is band-broadened by the amplitude-voltage converting unit 12.
    Type: Application
    Filed: November 10, 2010
    Publication date: October 11, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Masahiko Onishi
  • Publication number: 20110254624
    Abstract: A distortion compensation circuit capable of realizing highly accurate distortion compensation by updating a model even under a situation in which the appearance frequency of an input signal having a maximum value is low. A DPD processor 2 includes an inverse model estimation unit 22, which estimates an inverse model for a model expressing input-output characteristics of an HPA 6 based on an input signal S1 to the HPA 6 and an output signal S10 from the HPA 6, a distortion compensation unit 26, which compensates for distortion of the input-output characteristics by adding the inverse model to the input signal S1, and a sampling circuit 20, which samples the signals S2 and S10 in a predetermined time immediately before the sampling and inputs the signals S2 and S10 to the inverse model estimation unit 22.
    Type: Application
    Filed: October 19, 2009
    Publication date: October 20, 2011
    Inventor: Masahiko Onishi
  • Publication number: 20110254623
    Abstract: Disclosed is a distortion compensation circuit that efficiently compensates for distortion. A distortion compensation circuit (20) comprises a sampling memory unit (21), which accumulates an input signal and an output signal from an amplifier (4), a model estimation unit (22), which reads the input and output signals that are accumulated upon the sampling memory unit (21), estimates a model that represents an input/output characteristic of the amplifier (4), and outputs a coefficient that denotes the model thus estimated, and a distortion compensation unit (23), which compensates for a distortion of the amplifier (4), based on the coefficient.
    Type: Application
    Filed: September 30, 2009
    Publication date: October 20, 2011
    Inventors: Masahiko Onishi, Mikhail Illarionov
  • Patent number: 7947996
    Abstract: It is an important factor in application to the illumination field and the like to obtain a characteristic excellent in power efficiency in a light emitting element. The present invention provides a semiconductor light emitting element including: first and second conductive type semiconductor layers; first and second electrodes respectively provided on the same plane sides as the first and second conductive type semiconductor layers; and a light emitting structure, provided with the second electrode and including the first and second conductive type semiconductor layers, wherein the first electrode provided on an exposed surface of the first conductive type semiconductor layer at least has a translucent first layer and a reflective second layer, and the first layer has projecting portions projected from both sides of the second layer in a cross section of the element crossing over the light emitting structure and the first electrode.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: May 24, 2011
    Assignee: Nichia Corporation
    Inventors: Takahiko Sakamoto, Masahiko Onishi, Yoshiki Inoue
  • Publication number: 20100072501
    Abstract: A semiconductor light emitting device which includes at least one concave on a light extraction surface opposite to a surface on which a semiconductor stack comprising a light emitting layer between a n-type semiconductor layer and a p-type semiconductor layer is mounted. The concave has not less than two slopes each having a different slope angle in a direction that a diameter of the concave becomes narrower toward a bottom of the concave from an opening of the concave and a slope having a gentle slope angle is provided with irregularities and a slope having a steep slope angle is a flat surface.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 25, 2010
    Applicant: NICHIA CORPORATION
    Inventors: Yohei WAKAI, Masahiko ONISHI
  • Publication number: 20080142821
    Abstract: It is an important factor in application to the illumination field and the like to obtain a characteristic excellent in power efficiency in a light emitting element. The present invention provides a semiconductor light emitting element including: first and second conductive type semiconductor layers; first and second electrodes respectively provided on the same plane sides as the first and second conductive type semiconductor layers; and a light emitting structure, provided with the second electrode and including the first and second conductive type semiconductor layers, wherein the first electrode provided on an exposed surface of the first conductive type semiconductor layer at least has a translucent first layer and a reflective second layer, and the first layer has projecting portions projected from both sides of the second layer in a cross section of the element crossing over the light emitting structure and the first electrode.
    Type: Application
    Filed: June 27, 2007
    Publication date: June 19, 2008
    Applicant: NICHIA CORPORATION
    Inventors: Takahiko Sakamoto, Masahiko Onishi, Yoshiki Inoue