Abstract: A semiconductor device includes a first TFT of a first conductivity type and a second TFT of a second conductivity type. The first TFT includes a first semiconductor layer made of an oxide semiconductor material of the first conductivity type, a first gate insulating layer provided on the first semiconductor layer, a first gate electrode located opposite to a channel region of the first semiconductor layer with the first gate insulating layer interposed therebetween, and a first source electrode. The second TFT includes a second semiconductor layer made of an oxide semiconductor material of the second conductivity type or a transparent semiconductor material of the second conductivity type, a second gate insulating layer provided on the second semiconductor layer, a second gate electrode located opposite to a channel region of the second semiconductor layer with the second gate insulating layer interposed therebetween, and a second source electrode.

Abstract: In order to provide a novel determination device capable of determining the type of excretion by a subject and a related technology thereof, a determination device includes at least one processor, and the at least one processor carries out a determination process of determining the type of excretion by a subject by referring to a first gas concentration detected by a first gas sensor and a second gas concentration detected by a second gas sensor which differs from the first gas sensor in gas species to be mainly detected.

Abstract: An object of the present invention is to provide a cellulose acetate composition with excellent biodegradability and water solubility, and excellent thermoformability. A cellulose acetate composition comprising: a cellulose acetate having a degree of acetyl substitution of 0.4 or greater and less than 1.4; and a citrate ester-based plasticizer, wherein a content of the citrate ester-based plasticizer is 3 parts by weight or greater per 100 parts by weight of the total amount of the cellulose acetate and the citrate ester-based plasticizer.

Abstract: A generator is horizontally arranged in each plane central portion of horizontal frame bodies of a support frame body which is framed with the upper and lower horizontal frame bodies and a plurality of support poles, and a vertical main shaft of a vertical shaft rotor is integrally connected and supported between rotation shafts vertically facing each other of the upper and lower generators without using bearings to cooperatively move.

Abstract: An active matrix substrate includes a pixel TFT including an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, and a gate electrode disposed so as to face the oxide semiconductor layer with the gate insulating layer interposed therebetween, a plurality of gate lines, an interlayer insulating layer provided so as to cover the gate electrode and the plurality of gate lines, a plurality of source lines provided on the interlayer insulating layer, an upper insulating layer provided so as to cover the plurality of source lines, and an organic insulating layer provided on the upper insulating layer. The interlayer insulating layer includes a first layer formed of silicon oxide, a second layer provided on the first layer and formed of silicon nitride, and a third layer provided on the second layer and formed of silicon oxide.

Abstract: An active matrix substrate includes a first TFT having an oxide semiconductor layer formed from a first oxide semiconductor film and a second TFT having an oxide semiconductor layer formed from a second oxide semiconductor film. The oxide semiconductor layer of each TFT includes a high-resistance region including a channel region and offset regions and low-resistance regions including a source contact region, a drain contact region, and interposed regions. The first TFT has a gate insulating layer including a first insulating film and a second insulating film. The second TFT has a gate insulating layer including the second insulating film but not including the first insulating film. A total length L1 of the offset regions of the first TFT in a channel length direction is greater than a total length L2 of the offset regions of the second TFT in the channel length direction.

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

Abstract: A power supply apparatus (100) according to the present disclosure converts an input voltage supplied from a power source to a predetermined direct current voltage. The power supply apparatus (100) includes an inrush current prevention circuit (120) based on a buck converter system and configured to suppress a flow of inrush current from the power source to the power supply apparatus (100) and a boost converter circuit (130) configured to output the predetermined direct current voltage. A choke coil (104) included in the inrush current prevention circuit (120) and a choke coil (104) included in the boost converter circuit (130) are a common choke coil. A smoothing capacitor (107) included in the inrush current prevention circuit (120) and a smoothing capacitor (107) included in the boost converter circuit (130) are a common smoothing capacitor.

Abstract: A processing unit includes a direction decision unit and a guide information generation unit. The direction decision unit decides a direction in which a person who behaves without a sense of sight walks. The guide information generation unit generates guide information for the person who behaves without the sense of sight to walk in the decided direction. The present technology is applicable, for example, to a smartphone or the like used by the person who behaves without the sense of sight.

Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.

Abstract: A semiconductor device including a substrate, and a first circuit supported by the substrate and including a plurality of TFTs including a first TFT, wherein the first TFT includes a semiconductor layer, a lower gate electrode located on a side of the substrate of the semiconductor layer and overlapping a part of the semiconductor layer via a lower gate insulating layer, and an upper gate electrode located on a side opposite to the substrate of the semiconductor layer and overlapping a part of the semiconductor layer via an upper gate insulating layer, one of the lower gate electrode and the upper gate electrode is a first gate electrode and the other is a second gate electrode, a first signal is supplied to the first gate electrode, and a second signal different from the first signal is supplied to the second gate electrode, the first TFT has a threshold voltage between a high-level potential and a low-level potential of the first signal and between a high-level potential and a low-level potential of the sec

Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

Abstract: An active matrix substrate includes a first TFT and a second TFT, each of TFTs includes an oxide semiconductor layer and a gate electrode arranged on the oxide semiconductor layer with a gate insulating layer therebetween, in which in the first TFT, in the oxide semiconductor layer, in at least a part of a first region covered with the gate electrode with the gate insulating layer interposed therebetween, a layered structure including a high mobility oxide semiconductor film having a relatively high mobility and a low mobility oxide semiconductor film placed on the high mobility oxide semiconductor film and having a lower mobility than the high mobility oxide semiconductor film is provided, and in the second TFT, in a first region of the oxide semiconductor layer, throughout, of the high mobility oxide semiconductor film and the low mobility oxide semiconductor film, one oxide semiconductor film is provided, and the other oxide semiconductor film is not provided.

Abstract: An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs each including an oxide semiconductor layer, a lower gate electrode positioned on the substrate side of the oxide semiconductor layer, and an upper gate electrode positioned on the oxide semiconductor layer on a side opposite from the substrate, a plurality of source wiring lines extending in a column direction, a plurality of upper gate wiring lines extending in a row direction, and a plurality of lower gate wiring lines extending in the row direction. The plurality of lower gate wiring lines include a first gate wiring line, and the plurality of upper gate wiring lines include a second gate wiring line partially overlapping the first gate wiring line via the lower gate insulating layer and the upper gate insulating layer.

Abstract: A vertical shaft wind turbine that is superior in a rotational startability, even at a low wind speed, and is suited to a wind power generator that has high rotational torque. Each blade is an upper-and-lower-ends fixed type vertically long blade which is suitable for use as a wind turbine or a water turbine. The string length and thickness of an upper-and-lower-ends fixed type vertically long blade (8) that is fixed upper and lower ends to a vertical main shaft (7) gradually decrease from a main part (8) thereof to tips of the upper and lower inwardly curved inclined parts (8B, 8B), and a cross section of the main part (8A) is a lift type. A thickness of the cross-sectional shape is continuously and gradually thins from the main part (8) to the tips of the inwardly curved inclined parts (8B, 8B).

Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

Abstract: An active matrix substrate includes: a first oxide semiconductor layer including a first channel region; a first gate electrode disposed on the substrate side of the first oxide semiconductor layer; a channel protection layer disposed on a side of the first oxide semiconductor layer opposite to the substrate and covering the first channel region; a first TFT having a first source electrode and a first drain electrode in an upper layer of the channel protection layer; a second oxide semiconductor layer; a second gate electrode disposed on a side of the second oxide semiconductor layer opposite to the substrate; and the second TFT having a second source electrode and a second drain electrode disposed on an interlayer insulating layer that covers the second gate electrode, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are formed of the same layered oxide semiconductor film, the layered oxide semiconductor film has a layered structure including a high mobility oxide semicond