Patents by Inventor Masahiko Suzuki

Masahiko Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230258281
    Abstract: A valve V1 capable of detecting an operation abnormality has a magnet M1 that is attached in the vicinity of a pressing adapter 52 of a stem 53 that slides according to an opening/closing operation of the valve V1, and a magnetic sensor M2 that is attached to a surface acing the stem 53, inside the pressing adapter 52 that presses a peripheral edge of a diaphragm 51, and detects a change in a distance between the magnet M1 and the magnetic sensor M2. Further, an abnormality determination mechanism compares the change in the distance between the magnet M1 and the magnetic sensor M2 at the time of abnormality diagnosis detected by the magnetic sensor M2 and a previously measured change in the distance between the magnet M and the magnetic sensor M2 at the time of normality, and determines whether or not there is an abnormality.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 17, 2023
    Applicant: Fujikin Incorporated
    Inventors: Ryutaro Tanno, Kenji Aikawa, Akihiro Harada, Yuya Suzuki, Takahiro Matsuda, Katsunori Komehana, Masahiko Ochiishi, Tsutomu Shinohara
  • Publication number: 20230221605
    Abstract: A semiconductor device including a substrate, and a first circuit supported by the substrate and including a plurality of TFTs including a first TFT, wherein the first TFT includes a semiconductor layer, a lower gate electrode located on a side of the substrate of the semiconductor layer and overlapping a part of the semiconductor layer via a lower gate insulating layer, and an upper gate electrode located on a side opposite to the substrate of the semiconductor layer and overlapping a part of the semiconductor layer via an upper gate insulating layer, one of the lower gate electrode and the upper gate electrode is a first gate electrode and the other is a second gate electrode, a first signal is supplied to the first gate electrode, and a second signal different from the first signal is supplied to the second gate electrode, the first TFT has a threshold voltage between a high-level potential and a low-level potential of the first signal and between a high-level potential and a low-level potential of the sec
    Type: Application
    Filed: January 12, 2023
    Publication date: July 13, 2023
    Inventors: Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Hitoshi TAKAHATA, Takuya WATANABE, Tohru DAITOH
  • Publication number: 20230215876
    Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.
    Type: Application
    Filed: March 9, 2023
    Publication date: July 6, 2023
    Inventors: Masahiko SUZUKI, Tetsuo KIKUCHI, Hideki KITAGAWA, Setsuji NISHIMIYA, Kengo HARA, Hitoshi TAKAHATA, Tohru DAITOH
  • Publication number: 20230215877
    Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.
    Type: Application
    Filed: March 9, 2023
    Publication date: July 6, 2023
    Inventors: Kengo HARA, Tohru DAITOH, Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Hitoshi TAKAHATA
  • Publication number: 20230135065
    Abstract: An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs each including an oxide semiconductor layer, a lower gate electrode positioned on the substrate side of the oxide semiconductor layer, and an upper gate electrode positioned on the oxide semiconductor layer on a side opposite from the substrate, a plurality of source wiring lines extending in a column direction, a plurality of upper gate wiring lines extending in a row direction, and a plurality of lower gate wiring lines extending in the row direction. The plurality of lower gate wiring lines include a first gate wiring line, and the plurality of upper gate wiring lines include a second gate wiring line partially overlapping the first gate wiring line via the lower gate insulating layer and the upper gate insulating layer.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 4, 2023
    Inventors: Masahiko SUZUKI, Tetsuo KIKUCHI, Setsuji NISHIMIYA, Kengo HARA, Hitoshi TAKAHATA, Tohru DAITOH
  • Patent number: 11637132
    Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: April 25, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Tetsuo Kikuchi, Hideki Kitagawa, Setsuji Nishimiya, Kengo Hara, Hitoshi Takahata, Tohru Daitoh
  • Patent number: 11635058
    Abstract: A vertical shaft wind turbine that is superior in a rotational startability, even at a low wind speed, and is suited to a wind power generator that has high rotational torque. Each blade is an upper-and-lower-ends fixed type vertically long blade which is suitable for use as a wind turbine or a water turbine. The string length and thickness of an upper-and-lower-ends fixed type vertically long blade (8) that is fixed upper and lower ends to a vertical main shaft (7) gradually decrease from a main part (8) thereof to tips of the upper and lower inwardly curved inclined parts (8B, 8B), and a cross section of the main part (8A) is a lift type. A thickness of the cross-sectional shape is continuously and gradually thins from the main part (8) to the tips of the inwardly curved inclined parts (8B, 8B).
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: April 25, 2023
    Assignee: Global Energy Co. Ltd.
    Inventor: Masahiko Suzuki
  • Patent number: 11631704
    Abstract: An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: April 18, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kengo Hara, Tohru Daitoh, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Hitoshi Takahata
  • Publication number: 20230100273
    Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.
    Type: Application
    Filed: December 7, 2022
    Publication date: March 30, 2023
    Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
  • Publication number: 20230075289
    Abstract: An active matrix substrate includes: a first oxide semiconductor layer including a first channel region; a first gate electrode disposed on the substrate side of the first oxide semiconductor layer; a channel protection layer disposed on a side of the first oxide semiconductor layer opposite to the substrate and covering the first channel region; a first TFT having a first source electrode and a first drain electrode in an upper layer of the channel protection layer; a second oxide semiconductor layer; a second gate electrode disposed on a side of the second oxide semiconductor layer opposite to the substrate; and the second TFT having a second source electrode and a second drain electrode disposed on an interlayer insulating layer that covers the second gate electrode, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are formed of the same layered oxide semiconductor film, the layered oxide semiconductor film has a layered structure including a high mobility oxide semicond
    Type: Application
    Filed: August 25, 2022
    Publication date: March 9, 2023
    Inventors: Kengo HARA, Tohru DAITOH, Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Hitoshi TAKAHATA
  • Patent number: 11581340
    Abstract: An active matrix substrate is provided with a plurality of oxide semiconductor TFTs including a plurality of first TFTs. An oxide semiconductor layer of each oxide semiconductor TFT includes a channel region, a source contact region, and a drain contact region. In a view from a normal direction of the substrate, the channel region is a region located between the source contact region and the drain contact region and overlapping a gate electrode, and the channel region includes a first end portion and a second end portion that oppose each other and extend in a first direction from the source contact region side toward the drain contact region side, a source side end portion that is located on the source contact region side of the first and second end portions and extends in a second direction that intersects the first direction, and a drain side end portion that is located on the drain contact region side of the first and second end portions and extends in the second direction.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: February 14, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kengo Hara, Tohru Daitoh, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Hitoshi Takahata
  • Publication number: 20230014546
    Abstract: A vertical shaft wind turbine that is superior in a rotational startability, even at a low wind speed, and is suited to a wind power generator that has high rotational torque. Each blade is an upper-and-lower-ends fixed type vertically long blade which is suitable for use as a wind turbine or a water turbine. The string length and thickness of an upper-and-lower-ends fixed type vertically long blade (8) that is fixed upper and lower ends to a vertical main shaft (7) gradually decrease from a main part (8) thereof to tips of the upper and lower inwardly curved inclined parts (8B, 8B), and a cross section of the main part (8A) is a lift type. A thickness of the cross-sectional shape is continuously and gradually thins from the main part (8) to the tips of the inwardly curved inclined parts (8B, 8B).
    Type: Application
    Filed: September 20, 2022
    Publication date: January 19, 2023
    Inventor: Masahiko SUZUKI
  • Patent number: 11557679
    Abstract: An active matrix substrate has pixel regions, and includes a substrate, pixel TFTs disposed to respectively correspond to the pixel regions, and pixel electrodes electrically connected to the pixel TFTs. The pixel TFTs are each a top gate structure TFT that has an oxide semiconductor layer, a gate insulating layer on the oxide semiconductor layer, and a gate electrode opposing the oxide semiconductor layer with the gate insulating layer therebetween. The gate insulating layer is formed of silicon oxide and includes a lower layer contacting the oxide semiconductor layer, and an upper layer on the lower layer. The lower layer H/N ratio of hydrogen atoms to nitrogen atoms in the lower layer is 1.5 to 5.0. The upper layer H/N ratio of hydrogen atoms to nitrogen atoms in the upper layer is 0.9 to 2.0. The lower layer H/N ratio is larger than the upper layer H/N ratio.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: January 17, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Tohru Daitoh, Masahiko Suzuki, Setsuji Nishimiya, Kengo Hara, Hitoshi Takahata
  • Patent number: 11551629
    Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: January 10, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
  • Publication number: 20220406942
    Abstract: Each first thin film transistor of a semiconductor device includes: a lower electrode; a first oxide semiconductor layer including a channel region and first and second contact regions; a gate electrode disposed on the channel region with a gate insulating layer interposed therebetween; and a source electrode and a drain electrode connected to the first contact region and the second contact region, respectively. When viewed from a normal direction of the substrate, at least a part of the channel region overlaps the lower electrode, and at least one of the first and second contact regions is located outside the lower electrode. The channel region has a layered structure including a lower layer, an upper layer located between the lower layer and the gate insulating layer, and a high mobility layer disposed between the lower layer and the upper layer and having mobility higher than mobility of the lower layer and the upper layer.
    Type: Application
    Filed: June 8, 2022
    Publication date: December 22, 2022
    Inventors: Tetsuo KIKUCHI, Tohru DAITOH, Masahiko SUZUKI, Setsuji NISHIMIYA, Kengo HARA, Hitoshi TAKAHATA
  • Patent number: 11502115
    Abstract: An active matrix substrate includes a substrate, a first gate bus line, a second gate bus line, a third gate bus line, a first source bus line, a second source bus line, a first pixel region, a second pixel region, and a first source contact portion. When viewed from a normal direction of the substrate, a first opening portion is located between the second gate bus line and the third gate bus line, and a first distance D1 in a column direction between the second gate bus line and the first opening portion and a second distance D2 in the column direction between the third gate bus line and the first opening portion are both ? or more of a second interval Dy2 in the column direction between the second gate bus line and the third gate bus line.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: November 15, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Tetsuo Kikuchi, Setsuji Nishimiya, Kengo Hara, Hitoshi Takahata, Tohru Daitoh
  • Patent number: 11486353
    Abstract: A vertical shaft wind turbine that is superior in a rotational startability, even at a low wind speed, and is suited to a wind power generator that has high rotational torque. Each blade is an upper-and-lower-ends fixed type vertically long blade which is suitable for use as a wind turbine or a water turbine. The string length and thickness of an upper-and-lower-ends fixed type vertically long blade (8) that is fixed upper and lower ends to a vertical main shaft (7) gradually decrease from a main part (8) thereof to tips of the upper and lower inwardly curved inclined parts (8B, 8B), and a cross section of the main part (8A) is a lift type. A thickness of the cross-sectional shape is continuously and gradually thins from the main part (8) to the tips of the inwardly curved inclined parts (8B, 8B).
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: November 1, 2022
    Assignee: GLOBAL ENERGY CO., LTD.
    Inventor: Masahiko Suzuki
  • Publication number: 20220246105
    Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.
    Type: Application
    Filed: April 20, 2022
    Publication date: August 4, 2022
    Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
  • Patent number: 11393849
    Abstract: An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs, a plurality of gate bus lines, a plurality of source bus lines, and at least one trunk wiring provided in a non-display region and transmitting a signal, and a plurality of other wirings, each of which is disposed so as to at least partially overlap the trunk wirings. The active matrix substrate includes a first metal layer, a second metal layer disposed above the first metal layer, and a third metal layer disposed above the second metal layer on the substrate. One of the first, second, and third metal layers includes a source bus line, and other layer includes a gate bus line. The trunk wiring is formed in two metal layer of the first, second and third metal layers.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: July 19, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Tohru Daitoh, Hajime Imai, Masahiko Suzuki, Setsuji Nishimiya, Kengo Hara, Masamitsu Yamanaka, Hitoshi Takahata
  • Publication number: 20220208793
    Abstract: An active matrix substrate includes a first TFT having an oxide semiconductor layer formed from a first oxide semiconductor film and a second TFT having an oxide semiconductor layer formed from a second oxide semiconductor film. The oxide semiconductor layer of each TFT includes a high-resistance region including a channel region and offset regions and low-resistance regions including a source contact region, a drain contact region, and interposed regions. The first TFT has a gate insulating layer including a first insulating film and a second insulating film. The second TFT has a gate insulating layer including the second insulating film but not including the first insulating film. A total length L1 of the offset regions of the first TFT in a channel length direction is greater than a total length L2 of the offset regions of the second TFT in the channel length direction.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 30, 2022
    Inventors: Hitoshi TAKAHATA, Tetsuo KIKUCHI, Kengo HARA, Setsuji NISHIMIYA, Masahiko SUZUKI, Tohru DAITOH