Patents by Inventor Masahiko Suzuki

Masahiko Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190109155
    Abstract: An array substrate including a spin-on glass layer formed of spin-on glass material, a first line disposed on a lower side with respect to the spin-on glass layer, the first line including a copper containing layer formed of copper or a copper alloy and a metal upper layer formed of one selected from a group consisting of titanium, an aluminum alloy, a copper alloy, a tungsten alloy, and a tantalum alloy, and the metal upper layer disposed on the copper containing layer and disposed between the copper containing layer and the spin-on glass layer, and a second line disposed on an upper side with respect to the spin-on glass layer and overlapping the first line in a plan view.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 11, 2019
    Inventors: SETSUJI NISHIMIYA, TOHRU DAITOH, HAJIME IMAI, MASAHIKO SUZUKI, TETSUO KIKUCHI, TERUYUKI UEDA, KENGO HARA
  • Publication number: 20190101094
    Abstract: The present invention relates to a water turbine in which a unit pipe can be joined by an optional number and a rotating shaft integrated with a rotor can be joined by an optional number according to intended use or condition of use, and by which each rotor can be supported stably.
    Type: Application
    Filed: March 16, 2017
    Publication date: April 4, 2019
    Inventor: Masahiko SUZUKI
  • Publication number: 20190101097
    Abstract: A water turbine device is provided which can move a water turbine from a use position to a nonuse position with a light force, and which has a simplified structure. An intermediate portion of a suspension support rod for suspending a water turbine immersed in a flowing water in a waterway is pivotally attached to a platform provided on the waterway with a horizontal shaft, and a power generation device as a balance weight is provided at the free end of the suspension support rod, and the water turbine is rotatable around the horizontal shaft between the use position where the water turbine is immersed in a flowing water and the nonuse position above the flowing water.
    Type: Application
    Filed: March 9, 2017
    Publication date: April 4, 2019
    Inventor: Masahiko SUZUKI
  • Publication number: 20190103421
    Abstract: A TFT array substrate includes gate electrodes constructed from a first metal film, a first insulating film on the first metal film, channels constructed from a semiconductor film on the first insulating film, source electrodes constructed from a second metal film on the semiconductor film, drain electrodes constructed from the second metal film, pixel electrodes constructed from portions of the semiconductor film having reduced resistances, a second insulating film on the semiconductor film and the second metal film, and a common electrode constructed from a transparent electrode film on the second insulating film. The channels overlap the gate electrodes. The source electrodes and the drain electrodes are connected to first ends and second ends of the channels, respectively. The pixel electrodes are connected to the drain electrodes. The second insulating film includes sections overlapping the pixel electrodes without openings. The common electrode overlaps at least the pixel electrodes.
    Type: Application
    Filed: September 17, 2018
    Publication date: April 4, 2019
    Inventors: Tetsuo KIKUCHI, Tohru DAITOH, Hajime IMAI, Masahiko SUZUKI, Setsuji NISHIMIYA, Teruyuki UEDA, Kengo HARA
  • Publication number: 20190103494
    Abstract: A thin film transistor includes a channel section formed from semiconductor material, a source electrode connected to one end of the channel section, a drain electrode connected to another end of the channel section, an upper gate electrode included in an upper layer than the channel section and overlapping the channel section, a lower gate electrode included in a lower layer than the channel section and overlapping the channel section, an upper gate insulation film disposed between the upper gate electrode and the channel section, and a lower gate insulation film disposed between the lower gate electrode and the channel section and having a film thickness relatively greater than that of the upper gate insulation film.
    Type: Application
    Filed: September 26, 2018
    Publication date: April 4, 2019
    Inventors: Kengo HARA, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Teruyuki UEDA
  • Publication number: 20190097059
    Abstract: In a semiconductor device, at least one thin-film transistor includes a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, and a drain electrode. The semiconductor layer has a multilayer structure that includes a plurality of channel formation layers including a first channel formation layer and a second channel formation layer, and at least one middle layer including a first middle layer provided between the first channel formation layer and the second channel formation layer. The first channel formation layer is disposed closer to the gate insulating layer than is the second channel formation layer, and is in contact with the gate insulating layer. The plurality of channel formation layers and the at least one middle layer are all an oxide semiconductor layer. The plurality of channel formation layers each have a mobility higher than that of the at least one middle layer.
    Type: Application
    Filed: September 27, 2018
    Publication date: March 28, 2019
    Inventors: Tetsuo KIKUCHI, Tohru DAITOH, Hajime IMAI, Masahiko SUZUKI, Setsuji NISHIMIYA, Teruyuki UEDA, Kengo HARA
  • Patent number: 10243010
    Abstract: A semiconductor film 21 is provided so as to overlap with a light-shielding film 11 when viewed in a plan view. A second insulating film 30 has a contact hole CH1 that reaches a source electrode 22 and a drain electrode 23. A gate electrode 41 is provided on the second insulating film 30 so as to overlap with the semiconductor film 21 when viewed in a plan view, and at the same time, so as to overlap with none of the source electrode 22 and the drain electrode 23 when viewed in a plan view. A third insulating film 50 is provided on the second insulating film 30 so as to cover the gate electrode 41, and at the same time, so as to be in contact with the source electrode 22 and the drain electrode 23 through the contact hole CH1.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 26, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hajime Imai, Tohru Daitoh, Hisao Ochi, Tetsuo Fujita, Hideki Kitagawa, Tetsuo Kikuchi, Masahiko Suzuki, Teruyuki Ueda
  • Publication number: 20190081077
    Abstract: An active matrix substrate includes a substrate, a TFT-containing layer which is supported on the substrate, and which includes a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes of the TFT, a metal wiring layer which is supported on the substrate and has a thickness of 400 nm or more, and an inorganic insulating layer which is thinner than the metal wiring layer, and is arranged on a substrate side of the metal wiring layer and is in contact with a lower surface of the metal wiring layer. The metal wiring layer has tensile stress and the inorganic insulating layer has compressive stress, and a ratio Sb/Sa of an absolute value Sb of a stress value of the inorganic insulating layer to an absolute value Sa of a stress value of the metal wiring layer is 0.6 or more and 1.7 or less.
    Type: Application
    Filed: March 13, 2017
    Publication date: March 14, 2019
    Inventors: Masahiko SUZUKI, Tetsuo KIKUCHI, Hajime IMAI, Hisao OCHI, Hideki KITAGAWA, Setsuji NISHIMIYA, Toshikatsu ITOH, Teruyuki UEDA, Ryosuke GUNJI, Kengo HARA, Tohru DAITOH
  • Publication number: 20190055913
    Abstract: A hydraulic power generating apparatus which can be easily disposed in a water channel, such as a waterway or a water conducting pipe. The hydraulic power generating apparatus comprises a horizontal rotor supporting housing (4) having a rotor, a holding body (5) erected on an upper surface of the rotor supporting housing (4), a support ring (2) in which the rotor supporting housing (4) is fixed, and a power generator (11). The rotor supporting housing (4) is integrally fixed within the support ring (2) by the holding body (5). The power generator (11) is disposed on the upper part of the holding body (5) protruding from the support ring (2), and the support ring (2) is formed with attachment portions (2A, 2B) for fixing the rotor supporting housing (4) in a water channel.
    Type: Application
    Filed: December 7, 2016
    Publication date: February 21, 2019
    Applicant: Kabushiki Kaisha Bellsion
    Inventor: Masahiko SUZUKI
  • Publication number: 20190055918
    Abstract: A rotor blade for a wind power generator which is a lift type blade having a wide chord length at a blade end portion. The rotor blade (1) comprises a side surface with a thickness that gradually decreases from a blade root (1A) to a blade end portion, and a front surface (1D) which gradually inclines in a direction of a back surface (1E) from the blade root (1A) to the blade end portion. Owing to a difference in the thickness, a speed of airflow passing in a chord direction at the blade root, when the rotor blade is rotating, increases at the blade end portion, and air pressure at the blade root is reduces at the blade end portion, and airflow concentrating, due to the reduction of the air pressure at the blade root, naturally moves to the blade end portion due to a difference in the air pressure.
    Type: Application
    Filed: December 7, 2016
    Publication date: February 21, 2019
    Inventor: Masahiko SUZUKI
  • Publication number: 20190055927
    Abstract: Provided is a wind power generation method capable of efficiently generating electricity while preventing beforehand a rotor from stalling. A generator 3 is connected to a vertical main shaft 5 of a rotor 2 via a clutch 9. The method comprising following steps to be repeated; disconnecting the clutch when the rotor is rotating at or below a predetermined average wind speed, to idle the rotor, connecting the clutch for generating power by the generator when the rotor reached a specific peripheral speed or rotational speed, disconnecting the clutch again when the rotor is rotating at or below the predetermined average wind speed to idle the rotor until reach the specific value of peripheral speed or rotational speed, and connecting the clutch again for generating power by the generator when the rotor reached the specific value.
    Type: Application
    Filed: December 7, 2016
    Publication date: February 21, 2019
    Inventor: Masahiko SUZUKI
  • Publication number: 20190009873
    Abstract: It is an object of the present invention to provide a horizontal shaft rotor with low power and high rotation efficiency by achieving that a high-speed flow according to the Coanda effect caused by rotating the blade rather than pushing out the fluid with the blade flows to the back face direction and propulsive force is obtained as a reaction. A horizontal shaft rotor comprising a lift-type blade, wherein, in the lift-type blade 1, a front face 3D in a flow receiving direction is a large arcuate bulging face in a string direction, a rear face 3E in a discharge direction is made smaller than the bulge of the front face 3D, so that, when the blade rotates, a high speed flow passing along the string direction of the front face from the rear edge portion 3G to the back face 3E direction generates propulsive force.
    Type: Application
    Filed: February 22, 2017
    Publication date: January 10, 2019
    Inventor: Masahiko SUZUKI
  • Patent number: 10164118
    Abstract: A semiconductor device (100A) includes a substrate (101) and a thin film transistor (10) supported by the substrate. The thin film transistor includes a gate electrode (102), an oxide semiconductor layer (104), a gate insulating layer (103), a source electrode (105) and a drain electrode (106). The oxide semiconductor layer includes an upper semiconductor layer (104b) which is in contact with the source electrode and the drain electrode and which has a first energy gap, and a lower semiconductor layer (104a) which is provided under the upper semiconductor layer and which has a second energy gap that is smaller than the first energy gap. The source electrode and the drain electrode include a lower layer electrode (105a, 106a) which is in contact with the oxide semiconductor layer and which does not contain Cu, and a major layer electrode (105b, 106b) which is provided over the lower layer electrode and which contains Cu.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: December 25, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hisao Ochi, Tohru Daitoh, Hajime Imai, Tetsuo Fujita, Hideki Kitagawa, Tetsuo Kikuchi, Masahiko Suzuki, Shingo Kawashima
  • Patent number: 10141453
    Abstract: A semiconductor device (100) includes: a substrate (10); and a thin film transistor (5) supported on the substrate, the thin film transistor including a gate electrode (12), an oxide semiconductor layer (18), a gate insulating layer (20) provided between the gate electrode and the oxide semiconductor layer, and a source electrode (14) and a drain electrode (16) electrically connected to the oxide semiconductor layer, wherein: the drain electrode is shaped so as to project toward the oxide semiconductor layer; a width W1 and a width W2 satisfy a relationship |W1?W2|?1 ?m, where the width W1 is a width of the oxide semiconductor layer in a channel width direction of the thin film transistor, and the width W2 is a width of the drain electrode in a direction perpendicular to a direction in which the drain electrode projects; and the width W1 and the width W2 are 3 ?m or more and 6 ?m or less.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: November 27, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hajime Imai, Tohru Daitoh, Hisao Ochi, Tetsuo Fujita, Hideki Kitagawa, Tetsuo Kikuchi, Masahiko Suzuki, Shingo Kawashima
  • Patent number: 10134910
    Abstract: A semiconductor device (100A) includes: a substrate (1); a thin film transistor (101) whose active layer is an oxide semiconductor layer 5; at least one metal wiring layer including copper (7S, 7D); a metal oxide film including copper (8) arranged on an upper surface of the at least one metal wiring layer (7S, 7D); an insulating layer (11) covering at least one metal wiring layer with the metal oxide film (8) interposed therebetween; and a conductive layer (19) in direct contact with a portion of the at least one metal wiring layer, without the metal oxide film (8) interposed therebetween, in an opening formed in the insulating layer (11).
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: November 20, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Hajime Imai, Hisao Ochi, Tetsuo Fujita, Hideki Kitagawa, Tetsuo Kikuchi, Shingo Kawashima, Tohru Daitoh
  • Publication number: 20180329242
    Abstract: A spacer is fixed while an effect on a surface of an active matrix substrate is prevented. An active matrix substrate (1) includes a thin film transistor (11) which is provided on a substrate (2) and which has a recess made at a surface of the thin film transistor, and a spacer (13) fitted in the recess.
    Type: Application
    Filed: February 17, 2017
    Publication date: November 15, 2018
    Inventors: Hideki KITAGAWA, Tohru DAITOH, Hajime IMAI, Toshikatsu ITOH, Hisao OCHI, Tetsuo KIKUCHI, Masahiko SUZUKI, Teruyuki UEDA, Ryosuke GUNJI, Kengo HARA, Setsuji NISHIMIYA
  • Publication number: 20180277574
    Abstract: An active matrix substrate includes a first TFT (10), a second TFT (20) disposed per pixel, and a circuit including the first TFT. The first and second TFTs each include a gate electrode (102A, 102B), a gate insulating layer (103), an oxide semiconductor layer (104A, 104B), and source and drain electrodes in contact with an upper surface of the oxide semiconductor layer. The oxide semiconductor layer (104A, 104B) has a stacked structure including a first semiconductor layer (104e, 104c) in contact with the source and drain electrodes and a second semiconductor layer that is disposed on a substrate-side of the first semiconductor layer and that has a smaller energy gap than the first semiconductor layer. The oxide semiconductor layers (104A) and (104B) are different from each other in terms of the composition and/or the number of stacked layers. The first TFT has a larger threshold voltage than the second TFT.
    Type: Application
    Filed: January 26, 2017
    Publication date: September 27, 2018
    Inventors: Hisao OCHI, Tohru DAITOH, Hajime IMAI, Tetsuo FUJITA, Hideki KITAGAWA, Tetsuo KIKUCHI, Masahiko SUZUKI, Teruyuki UEDA
  • Publication number: 20180261628
    Abstract: A semiconductor film 21 is provided so as to overlap with a light-shielding film 11 when viewed in a plan view. A second insulating film 30 has a contact hole CH1 that reaches a source electrode 22 and a drain electrode 23. A gate electrode 41 is provided on the second insulating film 30 so as to overlap with the semiconductor film 21 when viewed in a plan view, and at the same time, so as to overlap with none of the source electrode 22 and the drain electrode 23 when viewed in a plan view. A third insulating film 50 is provided on the second insulating film 30 so as to cover the gate electrode 41, and at the same time, so as to be in contact with the source electrode 22 and the drain electrode 23 through the contact hole CH1.
    Type: Application
    Filed: November 28, 2016
    Publication date: September 13, 2018
    Inventors: Hajime IMAI, Tohru DAITOH, Hisao OCHI, Tetsuo FUJITA, Hideki KITAGAWA, Tetsuo KIKUCHI, Masahiko SUZUKI, Teruyuki UEDA
  • Publication number: 20180197959
    Abstract: A semiconductor device (100) is provided with a thin film transistor including an oxide semiconductor layer (5), a gate electrode (3), a gate insulating layer (4), and a source electrode (7s) and a drain electrode (7d) that are in contact with the oxide semiconductor layer, at least one electrode of the source electrode (7s), the drain electrode (7d), and the gate electrode (3) has a multilayer structure that includes a first layer (3A, 7A) containing copper and a second layer (3B, 7B) containing titanium or molybdenum, the thickness of the first layer (3A, 7A) is more than the thickness of the second layer (3B, 7B), when the source electrode (7s) or the drain electrode (7d) has the multilayer structure, the second layer is arranged on the oxide semiconductor layer side of the first layer so as to be in contact with the surface of the oxide semiconductor layer (5), when the gate electrode (3) has the multilayer structure, the second layer is arranged on the substrate (1) side of the first layer, and the thick
    Type: Application
    Filed: June 21, 2016
    Publication date: July 12, 2018
    Inventors: TETSUO FUJITA, HAJIME IMAI, HISAO OCHI, TETSUO KIKUCHI, HIDEKI KITAGAWA, MASAHIKO SUZUKI, SHINGO KAWASHIMA, TOHRU DAITOH
  • Patent number: 9926878
    Abstract: When a plunger of a high pressure pump is rising, a high pressure pump controller closes a regulator valve by energizing a solenoid of an electromagnetic actuator of the high pressure pump to discharge fuel into a delivery pipe. Further, this fuel discharge energization is stopped before the plunger reaches top dead center at a pump TDC timing. Further, a fuel pressure of the delivery pipe is detected at the pump TDC timing, and based on that detected value, a time Td from the pump TDC timing until a valve opening timing of the regulator valve is estimated. Once the estimated time Td elapses from the pump TDC timing, the solenoid is reenergized to removed a movement speed of a movable portion in a direction that pushes the regulator valve in an opening direction.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: March 27, 2018
    Assignee: DENSO CORPORATION
    Inventor: Masahiko Suzuki