Abstract: A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.

Abstract: A method for manufacturing the semiconductor device of which a transistor and a MNOS type memory transistor, each of which has a different gate withstand voltage and drain withstand voltage, are included in the same semiconductor layer.

Abstract: A fabrication method of a semiconductor device which has on the same semiconductor layer a transistor with a different high voltage gate as well as a high voltage drain and an MNOS memory transistor.

Abstract: A method of manufacturing a semiconductor device that has a high-breakdown-voltage transistor, a low-voltage driving transistor and a MONOS type memory transistor includes a step of forming a stack film that includes at least an oxide silicon layer and a nitride silicon layer over a high-breakdown-voltage transistor forming region where the high-breakdown-voltage transistor is formed, a low-voltage driving transistor forming region where the low-voltage driving transistor is formed and a MONOS type memory transistor forming region where the MONOS type memory transistor is formed in a semiconductor layer, a step of removing the stack film formed in a first gate insulating layer forming region of the high-breakdown-voltage transistor and a step of forming a first gate insulating layer in the high-breakdown-voltage transistor forming region by thermal oxidation.

Abstract: A semiconductor device is provided including a gate insulation layer formed on a semiconductor substrate, a source and drain region, an offset region composed of a doped layer of which concentration is low comparing to that of the source region and drain region and surrounds the source region and drain region, and a channel stopper region formed on the outside of the offset region. The channel stopper region includes a protrusion toward the long side direction of the gate insulation layer such that the distance between the gate insulation layer and the channel stopper region is narrower than the distance between the offset region and the channel stopper region.

Abstract: A fabrication method of a semiconductor device which has on the same semiconductor layer a transistor with a different high voltage gate as well as a high voltage drain and an MNOS memory transistor.

Abstract: A method for manufacturing the semiconductor device of which a transistor and a MNOS type memory transistor, each of which has a different gate withstand voltage and drain withstand voltage, are included in the same semiconductor layer.

Abstract: A semiconductor device manufacturing method is provided including: forming a first impurity layer that becomes first wells in a high breakdown voltage transistor forming region in a semiconductor layer; forming a second impurity layer that becomes offset regions in the high breakdown voltage transistor forming region; forming the first wells and the offset regions by diffusing impurities of the first and second impurity layers by heat treating the semiconductor layer; forming element isolation regions by a trench element isolation method in the semiconductor layer, after forming the first wells and the offset regions; forming first gate dielectric layers in the high breakdown voltage transistor forming region; forming second wells in a low voltage driving transistor forming region in the semiconductor layer; forming second gate dielectric layers in the low voltage driving transistor forming region; and forming gate electrodes in the high breakdown voltage transistor forming region and the low voltage driving

Abstract: A semiconductor device is provided that includes a semiconductor layer, first element isolation regions defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating an electric field of the high breakdown voltage transistors, wherein the high breakdown voltage transistors have gate dielectric layers formed by a CVD method.

Abstract: A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.

Abstract: Experiment shows that a diesel engine discharges more smoke at a lower rate of increase of an engine rotation speed. Reducing an amount of fuel to inject into the engine when the rate of increase of the engine rotation speed is slow can prevent smoke generation. To be more specific, a controller (1) computes the rate of increase of the engine rotation speed by using signals from sensors that detect a vehicle condition. The controller (1) contains maps that indicate a correction coefficient corresponding to the rate of increase of the engine rotation speed. The controller (1) calculates the amount of fuel to inject based on the correction coefficient. Using the calculated amount of fuel, the smoke discharge from the diesel engine is suppressed.

Abstract: Experiment shows that a diesel engine discharges more smoke at a lower rate of increase of an engine rotation speed. Reducing an amount of fuel to inject into the engine when the rate of increase of the engine rotation speed is slow can prevent smoke generation. To be more specific, a controller (1) computes the rate of increase of the engine rotation speed by using signals from sensors that detect a vehicle condition. The controller (1) contains maps that indicate a correction coefficient corresponding to the rate of increase of the engine rotation speed. The controller (1) calculates the amount of fuel to inject based on the correction coefficient. Using the calculated amount of fuel, the smoke discharge from the diesel engine is suppressed.

Abstract: A semiconductor device 100 has a substrate 11 including a high breakdown voltage transistor region where transistors with high breakdown voltage and high dielectric strength Qn and Qp are formed and a low breakdown voltage transistor region where transistors with low breakdown voltage and low dielectric strength are formed. The transistors with high voltage breakdown and high dielectric strength Qn and Qp and the transistors with low voltage breakdown and low dielectric strength operate at different voltages. In the high breakdown voltage transistor region, the semiconductor device has metal wiring layers 19a and 19b that are fed with a high potential. The metal wiring layers 19a and 19b are provided over the transistors with high voltage breakdown and high dielectric strength Qn and Qp through a first interlayer dielectric film 16 and a second interlayer dielectric film 17. An element isolation dielectric region 14 is provided over the substrate 11.

Abstract: A semiconductor device 100 has a substrate 11 including a high breakdown voltage transistor region where transistors with high breakdown voltage and high dielectric strength Qn and Qp are formed and a low breakdown voltage transistor region where transistors with low breakdown voltage and low dielectric strength are formed. The transistors with high voltage breakdown and high dielectric strength Qn and Qp and the transistors with low voltage breakdown and low dielectric strength operate at different voltages. In the high breakdown voltage transistor region, the semiconductor device has metal wiring layers 19a and 19b that are fed with a high potential. The metal wiring layers 19a and 19b are provided over the transistors with high voltage breakdown and high dielectric strength Qn and Qp through a first interlayer dielectric film 16 and a second interlayer dielectric film 17. An element isolation dielectric region 14 is provided over the substrate 11.