Patents by Inventor Masahiro Hosoda

Masahiro Hosoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160214169
    Abstract: The present invention provides fibrous copper microparticles suppressed in the occurrence of irregularities on the surface thereof and the aggregates of the fibrous copper microparticles having an average crystallite diameter controlled so as to fall within a specific range. In the fibrous copper microparticles of the present invention, the number of fibrous copper microparticles each including one or more irregularities each having a dimensional difference of 0.02 ?m or more, in a range of 1 ?m in the lengthwise direction of a fibrous body, between the maximum diameter portion of the fibrous body and the minimum diameter portion of the fibrous body falling in a diameter dimension range of 0.01 to 0.5 ?m, and each having a length of 1 ?m or more is 10 or less per 100 of the fibrous copper microparticles.
    Type: Application
    Filed: December 13, 2013
    Publication date: July 28, 2016
    Applicant: UNITIKA LTD.
    Inventors: Munenori Yamada, Kou Takeuchi, Mutsumi Matsushita, Airi Horikoshi, Akira Shigeta, Masahiro Hosoda, Yoshiaki Echigo, Kenta Shibata
  • Publication number: 20150147584
    Abstract: Fibrous copper microparticles having a minor axis of 1 ?m or less and an aspect ratio of 10 or more, wherein the content of the copper particles having a minor axis of 0.3 ?m or more and an aspect ratio of 1.5 or less is 0.1 or less copper particle per one fibrous copper microparticle.
    Type: Application
    Filed: June 11, 2013
    Publication date: May 28, 2015
    Applicant: UNITIKA LTD.
    Inventors: Munenori Yamada, Kou Takeuchi, Mutsumi Matsushita, Akira Shigeta, Masahiro Hosoda, Yoshiaki Echigo
  • Publication number: 20140120360
    Abstract: The present invention provides coated fibrous copper microparticles, wherein the coated fibrous copper microparticles are fibrous copper microparticles each at least partially coated with a metal other than copper, and the length and the aspect ratio of the fibrous copper microparticles are 1 ?m or more and 10 or more, respectively.
    Type: Application
    Filed: June 14, 2012
    Publication date: May 1, 2014
    Applicant: UNITIKA LTD.
    Inventors: Munenori Yamada, Akira Shigeta, Masahiro Hosoda, Yoshiaki Echigo
  • Patent number: 8262746
    Abstract: A production method for producing an electrode plate that can hold well the active material and producing a battery using the electrode plate. A production method for an electrode plate of a battery includes the steps of: forming at least one electrode plate prototype by forming a layer filled with an active material on a main surface of a plate-shaped core body; and infiltrating a liquid containing a resin and an organic solvent into at least part of a circumference of the layer filled with the active material. The applied liquid infiltrates into the circumferential region of the active material filling area, namely an outer edge of the layer and an area in its vicinity including the outer edge. The resin contained in the liquid enhances the bonding force between the conductive core body and the active material particles and between the active material particles.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: September 11, 2012
    Assignee: SANYO Electric Co., Ltd.
    Inventors: Katsuya Ito, Kazuhiro Yoshimura, Masahiro Hosoda
  • Patent number: 8242808
    Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: August 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Mitsuhiro Tomoeda, Makoto Muneyasu, Masahiro Hosoda
  • Publication number: 20110216620
    Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
    Type: Application
    Filed: May 12, 2011
    Publication date: September 8, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Mitsuhiro TOMOEDA, Makoto MUNEYASU, Masahiro HOSODA
  • Patent number: 7969200
    Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: June 28, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Mitsuhiro Tomoeda, Makoto Muneyasu, Masahiro Hosoda
  • Patent number: 7918673
    Abstract: Each of a pair of signal terminals (TC+ and TC?) includes a signal terminal link portion (uCON) that links a first signal terminal end portion (u1) and a second signal terminal end portion (u2). A ground terminal (TGC) includes a ground terminal link portion (tCON) that links a first ground terminal end portion (t1) and a second ground terminal end portion (t2). The ground terminal link portion (tCON) is wired between the signal terminal link portion (uCON) and a mounting surface (11A) from the opposite side of the mounting surface (11A) relative to the signal terminal link portion (uCON).
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: April 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Shouichi Mimura, Masato Tobinaga, Shinkuro Fujino, Ryuya Yamamoto, Masahiro Hosoda, Hirotsugu Fusayasu
  • Publication number: 20100301902
    Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
    Type: Application
    Filed: July 28, 2010
    Publication date: December 2, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Mitsuhiro TOMOEDA, Makoto Muneyasu, Masahiro Hosoda
  • Patent number: 7795922
    Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: September 14, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Mitsuhiro Tomoeda, Makoto Muneyasu, Masahiro Hosoda
  • Publication number: 20090237114
    Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
    Type: Application
    Filed: January 29, 2009
    Publication date: September 24, 2009
    Inventors: Mitsuhiro TOMOEDA, Makoto MUNEYASU, Masahiro HOSODA
  • Publication number: 20080044724
    Abstract: The aim is to provide a sealed secondary battery with an electrode body that is larger in volume and thus incapacity, without affecting the operability of a valve member and the battery hermeticity. To achieve the aim, the sealed secondary battery includes an electrode body, an external casing, a closure plate, and a valve member. The external casing is of a tubular shape having a bottom and an opening. The closure plate has a hole formed through a central portion thereof and is secured at a peripheral portion to the edge of the opening of the external casing. The valve member has a resilient portion and a plate portion. The plate portion is biased by the resilient portion against the closure plate to close off the hole. The closure plate is smaller in average thickness at portions opposite a main surface of the plate portion than at other portions.
    Type: Application
    Filed: March 30, 2007
    Publication date: February 21, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Hiroyuki Inoue, Masahiro Hosoda, Takaaki Aoto
  • Patent number: 7226693
    Abstract: A method for producing a cadmium negative electrode for alkaline batteries according to the present invention comprises a step of obtaining a cadmium active-substance impregnated electrode plate by impregnating said electrode substrate with a cadmium active substance; and a step of adding polyethylene glycol for forming a polyethylene glycol coating on the surface of said cadmium negative electrode or on the surface of said active substance by coating or impregnating said active-substance impregnated electrode with polyethylene glycol.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: June 5, 2007
    Assignee: Sanyo Electronic Co., Ltd.
    Inventors: Kei Tomihara, Masahiro Hosoda
  • Publication number: 20070062029
    Abstract: A production method for producing an electrode plate that can hold well the active material and producing a battery using the electrode plate. A production method for an electrode plate of a battery includes the steps of: forming at least one electrode plate prototype by forming a layer filled with an active material on a main surface of a plate-shaped core body; and infiltrating a liquid containing a resin and an organic solvent into at least part of a circumference of the layer filled with the active material. The applied liquid infiltrates into the circumferential region of the active material filling area, namely an outer edge of the layer and an area in its vicinity including the outer edge. The resin contained in the liquid enhances the bonding force between the conductive core body and the active material particles and between the active material particles.
    Type: Application
    Filed: August 24, 2006
    Publication date: March 22, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Katsuya Ito, Kazuhiro Yoshimura, Masahiro Hosoda
  • Patent number: 7074482
    Abstract: An antibacterial polyamide filament which comprises a polyamide resin containing 0.1 to 5.0 mass % of fine zinc oxide particles and exhibits a color difference caused by the treatment with an alkaline solution of 2.5 or less; and a method for producing the antibacterial polyamide filament which comprises adjusting the moisture content of a polyamide resin chip to 0.05 to 2.0 mass %, followed by melt spinning. Preferably, the antibacterial polyamide filament has a bacteriostatic activity after 50 washings of 2.2 or more, which filament can be produced by melt-spinning the polyamide resin to melt spinning and solidifying the resin at a position 400 mm or less from the face of a spinning nozzle.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: July 11, 2006
    Assignee: Unitika Fibers Ltd.
    Inventors: Masaki Nishimura, Takeshi Nishiyama, Mitsuo Omori, Eiji Tsukamoto, Seiji Abe, Masahiro Hosoda, Hideharu Yamamoto, Minoru Fujii, Shuhei Kurata, Kunio Akasaki
  • Patent number: 7056028
    Abstract: A combination seal ring with an encoder for use to close off the opening of the space between a fixed ring and a rotational ring and to detect a rotational speed of the rotational ring, comprising a seal ring secured to the fixed ring, a metal slinger secured to the rotational ring, and an encoder of a rubber magnet secured to the slinger, the seal ring comprising a metal core secured to the fixed ring, and a fixed ring portion bent toward the rotational ring from the fixed cylindrical portion; and a resilient member bonded all around the metal core, the slinger comprising a rotational cylindrical portion secured to the rotational ring, and a rotational ring portion bent toward the fixed ring from the rotational cylindrical portion, the encoder bonded on the rotational circular ring portion, opposite to the seal lips by a molding process, the end rim of the encoder being short at least 0.2 mm of the end rim of the rotational circular ring portion.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: June 6, 2006
    Assignee: NSK Ltd.
    Inventors: Masahiro Hosoda, Yuji Nakamura
  • Patent number: 6738402
    Abstract: By using a single semiconductor laser device, laser beams in infrared and red regions are generated at a distance between close light emitting spots. A semiconductor laser resonator having an oscillation wavelength in an infrared region and a semiconductor laser resonator having an oscillation wavelength in a red region are formed in parallel on the same semiconductor substrate.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: May 18, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Hosoda, Tadashi Takeoka, Atsuo Tsunoda
  • Publication number: 20040036226
    Abstract: A combination seal ring with an encoder for use to close off the opening of the space between a fixed ring and a rotational ring and to detect a rotational speed of the rotational ring, comprising a seal ring secured to the fixed ring, a metal slinger secured to the rotational ring, and an encoder of a rubber magnet secured to the slinger, the seal ring comprising a metal core secured to the fixed ring, and a fixed ring portion bent toward the rotational ring from the fixed cylindrical portion; and a resilient member bonded all around the metal core, the slinger comprising a rotational cylindrical portion secured to the rotational ring, and a rotational ring portion bent toward the fixed ring from the rotational cylindrical portion, the encoder bonded on the rotational circular ring portion, opposite to the seal lips by a molding process, the end rim of the encoder being short at least 0.2 mm of the end rim of the rotational circular ring portion.
    Type: Application
    Filed: August 26, 2003
    Publication date: February 26, 2004
    Applicant: NSK Ltd.
    Inventors: Masahiro Hosoda, Yuji Nakamura
  • Patent number: 6682076
    Abstract: A combination seal ring with an encoder for use to close off the opening of the space between a fixed ring and a rotational ring and to detect a rotational speed of the rotational ring, comprising a seal ring secured to the fixed ring, a metal slinger secured to the rotational ring, and an encoder of a rubber magnet secured to the slinger, the seal ring comprising a metal core secured to the fixed ring, and a fixed ring portion bent toward the rotational ring from the fixed cylindrical portion; and a resilient member bonded all around the metal core, the slinger comprising a rotational cylindrical portion secured to the rotational ring, and a rotational ring portion bent toward the fixed ring from the rotational cylindrical portion, the encoder bonded on the rotational circular ring portion, opposite to the seal lips by a molding process, the end rim of the encoder being short at least 0.2 mm of the end rim of the rotational circular ring portion.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: January 27, 2004
    Assignee: NSK Ltd.
    Inventors: Masahiro Hosoda, Yuji Nakamura
  • Patent number: 6534215
    Abstract: The present invention discloses a sintered cadmium negative electrode for use in an alkaline storage battery having a porous sintered nickel substrate and an active material containing cadmium hydroxide, the active material impregnated in the porous sintered nickel substrate, sintered cadmium negative electrode in which a groove 3 having a depth of 0.1 to 20 &mgr;m is provided on a surface of the substrate so that a projected region and a depressed region are formed on the surface of the substrate. An alkaline storage battery employing the sintered cadmium negative electrode of the invention achieves, as well as a high capacity, an improved large current charge-discharge characteristic by increasing an oxygen gas absorbing performance.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: March 18, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshitaka Shinyashiki, Akira Hirakawa, Masahiro Hosoda