Abstract: A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

Abstract: An improved buffer circuit is provided having an output stage for driving a load and a driver stage for driving said output stage. The output stage is constituted by a first MOS transistor to avoid problems found in bipolar output transistors which result from the amplitude of the output stage being influenced by the voltage V.sub.be of such output bipolar transistors. The driver stage, on the other hand, is formed of a bipolar transistor-MOS transistor composite logic cirucit. This driver stage includes an output circuit having a bipolar transistor for driving said first MOS transistor, and an input circuit including a second MOS transistor responsive to a predetermined input for rendering said bipolar transistor in the on or off state. The channel size of said first MOS transistor is larger than that of said second MOS transistor to give a device having an improved high operating speed.

Abstract: A bipolar/CMOS mixed type switching circuit comprising two npn-type bipolar transistors Q.sub.1, Q.sub.2 that are connected in the form of a totem pole in the output stage, a CMOS inverter and an NMOSFET M.sub.3 for driving these transistors in a complementary manner, and resistance means R for discharging the electric charge stored in the base of the transistor Q.sub.2. The threshold voltage of an NMOSFET M.sub.2 constituting the CMOS inverter in the absence of substrate effect is set to be substantially equal to the threshold voltage of the NMOSFET M.sub.3 in the absence of the substrate effect, and the channel conductance W.sub.N /L.sub.N of the NMOSFET M.sub.3 is so set that the threshold voltage V.sub.LT1 of the CMOS inverter and the practical threshold voltage V.sub.LT2 of the NMOSFET M.sub.3 will be nearly the same. Owing to the above structure, there is obtained a switching circuit which permits little through current to flow and which operates at high speeds.

Abstract: In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

Abstract: A switching circuit comprises a pre-stage circuit coupled to receive an input signal and an output stage, wherein an output signal having a phase opposite to that of a signal of an input terminal IN can be obtained from an output terminal OUT of the output stage. The pre-stage circuit includes a p-channel MOSFET M1 and an n-channel MOSFET M2 that receive input signals at their gates. The output stage includes two NPN transistors Q1 and Q2 that are connected in series. The drain output of the p-channel MOSFET M1 is applied to the base of one of the transistors of the output stage, and the source output of the n-channel MOSFET M2 is applied to the base of the other of the transistors of the output stage. A third MOSFET M3 is coupled between a power supply and the p-channel MOSFET M1 and the n-channel MOSFET M2. When the MOSFET M3 is rendered non-conductive by a control signal EN, both MOSFETs M1 and M2 and both NPN transistors Q1 and Q2 become non-conductive irrespective of the signal of the input terminal IN.

Abstract: A novel composite circuit comprises a first bipolar transistor with a collector of a first conductivity type connected to a first potential, an emitter of the first conductivity type connected to an output, a second bipolar transistor with a collector of the first conductivity type connected to the output and an emitter of the first conductivity type connected to a second potential, a field effect transistor of a second conductivity type with a gate connected to an input, a source connected to a third potential and a drain connected to the base of the first bipolar transistor, a field effect transistor of the first conductivity type with a gate connected to the input, a drain connected to the base of the first bipolar transistor, and a source connected to the base of the second bipolar transistor, and a unidirectional element inserted between the output and the drain of the field effect transistor of the first conductivity type and having a direction of rectification opposite to that of the PN junction formed

Abstract: Disclosed is a raster scanning type CRT display apparatus having a microprogrammed processor for primarily controlling the input and output of data to and from an external information source. This CRT display apparatus comprises a plurality of cursor controlling registers having their contents set by the processor. The contents of these registers define the configuration of a cursor for displaying a data entry position on its screen, the decision with respect to the blinking of the cursor, and a period of the blinking.

Abstract: Disclosed is a CRT display apparatus of a raster scanning type which includes a microprocessor as a unit for data handling or processing in an input/output control part for controlling data transfer with a computer and/or keyboard, the operations of the microprocessor being controlled by a microprogram stored in a microprogram memory. A timing control unit or part for producing various timing signals for controlling displays is connected to the microprocessor through a data bus and an address bus so that control parameter for the various timing operations can be set through the microprogram. The timing control part comprises programmable control registers, counters for generating timing signals and coincidence detectors or comparators for detecting coincidence between the outputs from the control registers and the timing signals from the associated counters.

Abstract: A raster scan type CRT display system is disclosed which has a randomly accessable refresh memory. The display system comprises column and row start address registers for defining a read start address for the refresh memory, column and row address counters for counting the contents of the column and row start address registers as start positions to generate a read address of the refresh memory for display, column and row cursor registors for defining a data entry position on a CRT screen, and column and row address generators for generating an entry address for the refresh memory based on the contents of the column and row start address registers and the contents of the column and row cursor registers, whereby a rolling or shifting of the image is effected and the refresh memory can be accessed by a processor for read/write operation without the need to monitor the image rolling.

Abstract: A light pen detection system used for a display system using a cathode ray tube (CRT) in which the operation for detecting the character display position on the CRT face is started when the operation switch of the light pen is turned on, and repeatedly progresses in synchronism with the picture repetition rate, and when a position marker is displayed at the character display position detected through such detecting operation, the operation switch of the light pen is turned off thereby to stop such detecting operation, whereby the character display position detected is obtained as the up-to-date one indicated by the light pen.