Abstract: The invention is intended to provide a control device for a vehicular AC motor, which has higher efficiency of voltage utilization in a power running mode and has higher efficiency of electricity generation in an electricity generation mode. The motor control device comprises rectifying devices and switching devices for three phases, which are connected between a DC power source and armature coils of an AC motor operatively coupled to an internal combustion engine. The motor control device has the inverter function of converting a DC power from the DC power source into an AC power and supplying the AC power to the armature coils, and the converter function of converting an AC power generated by the AC motor into a DC power and supplying the DC power to the DC power source.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1, And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K1.

Abstract: In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.

Abstract: A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.

Abstract: In a driving apparatus of a power semiconductor element for conducting or interrupting a main current, first resistance variable for changing a first resistance according to a control voltage, and second resistance variable for changing a second resistance according to a voltage between a first and a second terminal are provided, and either one of a voltage of a control power supply or a voltage between the first and the second terminal is voltage-divided by the first resistance and the second resistance, and the divided voltage is applied to a control gate terminal at the time of conducting or interrupting the main current.

Abstract: In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.

Abstract: In a driving apparatus of a power semiconductor element for conducting or interrupting a main current, first resistance variable for changing a first resistance according to a control voltage, and second resistance variable for changing a second resistance according to a voltage between a first and a second terminal are provided, and either one of a voltage of a control power supply or a voltage between the first and the second terminal is voltage-divided by the first resistance and the second resistance, and the divided voltage is applied to a control gate terminal at the time of conducting or interrupting the main current.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1. and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.

Abstract: A power inverter using a voltage driven switching element, capable of suppressing an excessive surge voltage which is generated on high-speed switching of IGBTs or MOSFETs, and suppressing radio frequency oscillation after the suppression of the surge voltage. The power inverter includes a switching element rendering a power path conducting and non-conducting, and a speeding-up circuit of a feedback path in an active clamping circuit added to the switching element.

Abstract: In a driving apparatus of a power semiconductor element for conducting or interrupting a main current, first resistance variable for changing a first resistance according to a control voltage, and second resistance variable for changing a second resistance according to a voltage between a first and a second terminal are provided, and either one of a voltage of a control power supply or a voltage between the first and the second terminal is voltage-divided by the first resistance and the second resistance, and the divided voltage is applied to a control gate terminal at the time of conducting or interrupting the main current.

Abstract: In a driving apparatus of a power semiconductor element for conducting or interrupting a main current, first resistance variable for changing a first resistance according to a control voltage, and second resistance variable for changing a second resistance according to a voltage between a first and a second terminal are provided, and either one of a voltage of a control power supply or a voltage between the first and the second terminal is voltage-divided by the first resistance and the second resistance, and the divided voltage is applied to a control gate terminal at the time of conducting or interrupting the main current.

Abstract: In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.

Abstract: A driver circuit wherein a first switching element and a second switching element are totem-pole-connected, wherein the totem pole connection is connected at its one end, node and other end with a power source, an output to a load and a reference potential, respectively, wherein the first switching element is connected between the one end and the node, wherein the second switching element is connected between the node and the other end, and wherein a third switching element is connected between the one end of the totem pole connection and the control terminal of the first switching element.

Abstract: A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.

Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

Abstract: A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

Abstract: An electric apparatus has a plurality of electric parts and a casing made of electrically conductive material for accommodating therein or mounting thereon a plurality of electric parts. The casing, which has a cavity therein, is provided with a plurality of projections for radiating heat generated by the electric parts in the cavity. The casing is provided with openings for allowing a heat conductive medium to flow into and out of the casing. Further, an electric apparatus has a plurality of electric parts and a casing made of electrically conductive material for accommodating therein or mounting thereon a plurality of electric parts. The casing is provided with openings for allowing a heat conductive medium to flow into and out of the casing. The casing is provided therein with a partition wall which is made of electrically conductive material for dividing the interior of the casing into a plurality of zones along a direction of a flow of the heat conductive medium.

Abstract: A semiconductor device is provided which comprises a memory mat formed by dividing a memory into a plurality of blocks and a circuit arrangement disposed at every memory mat block for generating access suppression signals at least for defective memory cells within that block. Using this arrangement, the access speed to a redundant memory cell array for relieving the defects is increased so that a semiconductor memory device capable of a high speed operation is obtained.

Abstract: A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.