Abstract: A multiprocessor having a plurality of processor elements connected in a cascaded manner. A memory is shared between each processor element and a processor adjacent in an upper or lower rank to the processor. In the lower processor element, there are disposed an arbiter for arbitrating a memory access with its upper processor element and a bus selector for switching a bus with the arbiter. The processor elements are connected in a multistage tree structure by a bus connection only. From the upper processor element, therefore, there can be accessed the shared memory in the lower processor element only through an external bus. The whole system is not limited by the address space of each processor and the bus, even if the address space is finite, so that the real memory capacity can be limitlessly expanded in a manner to correspond to the internal memory of each processor element.

Abstract: In an adder control circuit, a plurality of full adders are so arranged that a carry bit of the full adder for calculating low orders of values to be added is inputted to the full adder for calculating high orders thereof. In this case, the addresses are controlled in response to a clock having a time period which is more than a maximum calculation time period among calculation time periods by the respective full adders required for outputting the carry bits, and is less than a total calculation time period of all full adders.

Abstract: A method of processing a plurality of different code systems for an information processing apparatus including an operating system, comprises a step of inputting a source program, and a compiling step of analyzing meaning of the source program to thereby create a series of instructions and data required for executing a processing equivalent to the meaning of the source program.

Abstract: A data processing system having a first storage for storing therein microprograms; an address register for supplying an instruction address of a microprogram to be executed into said first storage; a stack unit having a stack area for storing therein a return address of the microprogram; a first control unit responsive to a microinstruction for instructing a microsubroutine call to store the return address of the microinstruction in the stack unit, and responsive to a microinstruction for instructing return from the microsubroutine to restore the return address of the microinstruction from said stack unit; a second control unit for monitoring an interrupt request; a second storage for saving therein the content of said stack unit; a status register having a field for indicating the acceptance of the interrupt request in the course of the execution of the microprogram, and a third control unit responsive to the detection of the interrupt request by the second control unit in the course of the execution of the