Patents by Inventor Masahiro Kanazawa

Masahiro Kanazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10319485
    Abstract: A radioprotective unwoven fabric is a sheet in which metal fibers are three-dimensionally and randomly stacked, the metal fibers each comprising a metal material having a specific gravity higher than a specific gravity of lead. The metal fibers may comprise a tungsten wire.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 11, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO, LTD.
    Inventors: Kazushige Sugita, Masahiro Matsumoto, Tomohiro Kanazawa, Tsuyoshi Terada
  • Publication number: 20190173240
    Abstract: An in-vehicle control system includes a power distribution box which supplies electric power to a downstream side, an in-vehicle device having one or more loads, and a connection cable which connects the power distribution box to the in-vehicle device disposed in the downstream side of the power distribution box. The power distribution box includes a host controller. At least one connector attached to the connection cable includes a connector control unit. The host controller acquires via the connection cable and holds connector identification information previously assigned to the connector control unit.
    Type: Application
    Filed: December 3, 2018
    Publication date: June 6, 2019
    Inventors: Masashi Nakamura, Masahiro Furukawa, Satoshi Enomoto, Akiyoshi Kanazawa
  • Publication number: 20190168692
    Abstract: A circuit body for a vehicle is wired on a vehicle body of the vehicle for performing supply of electric power to an electrical component and communication of various communication signals with the electrical component. The circuit body includes: a plurality of control boxes separately disposed on the circuit body and capable of controlling input and output of at least one of the electric power and the communication signal; a trunk line harness connecting one of the plurality of control boxes and another of the plurality of control boxes; and a branch line harness connecting the control box and the electrical component. At least one of the plurality of control boxes is grounded via the electrical component connected to the branch line harness.
    Type: Application
    Filed: November 21, 2018
    Publication date: June 6, 2019
    Inventors: Masashi Nakamura, Masahiro Furukawa, Satoshi Enomoto, Akiyoshi Kanazawa
  • Publication number: 20190168695
    Abstract: A circuit body for a vehicle is wired on a vehicle body of the vehicle for performing supply of electric power to an electrical component and communication of various communication signals with the electrical component. The circuit body includes: a plurality of control boxes separately disposed on the circuit body and capable of controlling input and output of at least one of the electric power and the communication signal; a trunk line harness connecting one of the plurality of control boxes and another of the plurality of control boxes; and a branch line harness connecting the control box and the electrical component. The trunk line harness includes a power line for transmitting electric power and a communication line for transmitting communication signals in a separated state. An end portion of the power line and an end portion of the communication line are connected to the control box.
    Type: Application
    Filed: December 3, 2018
    Publication date: June 6, 2019
    Inventors: Masashi Nakamura, Masahiro Furukawa, Satoshi Enomoto, Akiyoshi Kanazawa
  • Publication number: 20190168693
    Abstract: A circuit body for a vehicle includes: a plurality of control boxes capable of controlling input and output of at least one of electric power and a communication signal; a trunk line harness connecting one of the plurality of control boxes and another of the plurality of control boxes; and a branch line harness connecting the control box and the electrical component. The control box includes: a trunk line connecting portion to which the trunk line harness is connected; and a branch line connecting portion to which the branch line harness is connected. At least one of the trunk line connecting portion and the branch line connecting portion includes a plurality of connectors which are classified into a plurality of groups according to an allowable current amount and in which a plurality of the connectors classified into the same group have connection compatibility.
    Type: Application
    Filed: November 21, 2018
    Publication date: June 6, 2019
    Inventors: Masashi Nakamura, Masahiro Furukawa, Satoshi Enomoto, Akiyoshi Kanazawa
  • Publication number: 20190168698
    Abstract: A circuit body for a vehicle is wired on a vehicle body of the vehicle for performing supply of electric power to an electrical component and communication of various communication signals with the electrical component. The circuit body includes: a plurality of control boxes separately disposed on the circuit body and capable of controlling input and output of at least one of the electric power and the communication signal; a trunk line harness connecting one of the plurality of control boxes and another of the plurality of control boxes; and a branch line harness connecting the control box and the electrical component. The circuit body has a loop structure in which at least part of the plurality of control boxes are annularly connected via the trunk line harness.
    Type: Application
    Filed: November 21, 2018
    Publication date: June 6, 2019
    Inventors: Masashi Nakamura, Masahiro Furukawa, Satoshi Enomoto, Akiyoshi Kanazawa
  • Patent number: 7216329
    Abstract: An automatic circuit design apparatus includes a setting module configured to set an upper limit electric potential of a virtual ground line in a circuit to be designed, by use of a cell library for low-threshold cells, a cell library for high-threshold cells, and information of the circuit to be designed. A layout generator is configured to generate a layout based on the information, the cell library for low-threshold cells, and the cell library for high-threshold cells.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: May 8, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kitahara, Masaaki Yamada, Naoyuki Kawabe, Masahiro Kanazawa, Katsuhiro Seta, Toshiyuki Furusawa
  • Patent number: 7109771
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: September 19, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20060177808
    Abstract: An ability evaluation apparatus which evaluates an individual ability and stores a result of evaluation in an ability database, includes an ability mapping rule storing unit that stores an ability mapping rule which associates an ability item extracted from an ability sentence written in a natural language about an individual ability with a data item in the ability database using a structure of the ability sentence, a natural language processing unit that analyzes each sentence in a document written in the natural language about the individual ability to output a result of structural analysis, and an ability item storing unit that extracts the ability item from the result of structural analysis output from the natural language processing unit using the ability mapping rule stored in the ability mapping rule storing unit, and stores the extracted ability item in the ability database.
    Type: Application
    Filed: January 24, 2006
    Publication date: August 10, 2006
    Inventors: Hidenori Aosawa, Masahiro Kanazawa
  • Patent number: 7088161
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: August 8, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20050097494
    Abstract: An automatic circuit design apparatus includes a setting module configured to set an upper limit electric potential of a virtual ground line in a circuit to be designed, by use of a cell library for low-threshold cells, a cell library for high-threshold cells, and information of the circuit to be designed. A layout generator is configured to generate a layout based on the information, the cell library for low-threshold cells, and the cell library for high-threshold cells.
    Type: Application
    Filed: April 2, 2004
    Publication date: May 5, 2005
    Inventors: Takeshi Kitahara, Masaaki Yamada, Naoyuki Kawabe, Masahiro Kanazawa, Katsuhiro Seta, Toshiyuki Furusawa
  • Patent number: 6864720
    Abstract: A semiconductor integrated circuit is disclosed, which comprises a tree structure of buffer circuit groups configured to have an enable-signal-controlled AND buffer circuit at least in a final stage, a latch circuit provided in a correspondence to the enable-signal-controlled AND buffer circuit and configured to receive an enable signal and clock signal and deliver an output to an input portion of a final stage buffer circuit, an enable-signal-controlled AND buffer circuit provided in a portion of an intermediate stage of the buffer circuit groups, and an OR circuit provided in a correspondence to the intermediate stage enable-signal-controlled AND buffer circuit and configured to take a logical sum of a plurality of enable signals for controlling the operations of a plurality of enable-signal-controlled AND buffer circuits more on a load circuit side and deliver a logical sum output to an input portion of the intermediate stage enable-signal-controlled AND buffer circuit.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: March 8, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiro Kanazawa
  • Patent number: 6861882
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: March 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20050035802
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Application
    Filed: September 21, 2004
    Publication date: February 17, 2005
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Publication number: 20050035803
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Application
    Filed: September 23, 2004
    Publication date: February 17, 2005
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa
  • Patent number: 6813750
    Abstract: A logic circuit design equipment and a logic circuit design method include analyzing input states of all of first cells, respectively, analyzing leakage currents of all of first cells in a case where each first cell is high Vth cell showing a small leakage current at a low speed operation and low Vth cell showing a large leakage current at a high speed operation, respectively, and substituting the first cells for second cells within a range satisfying a timing restriction. Herein, a threshold of the second cell is different from a threshold of the first cell.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: November 2, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kimiyoshi Usami, Naoyuki Kawabe, Takeshi Kitahara, Masahiro Kanazawa
  • Patent number: 6750680
    Abstract: There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced. In a semiconductor integrated circuit according to the present invention, only a gate circuit on a critical path is constituted by an MT gate cell obtained by combining transistors having a low threshold voltage with transistors having a high threshold voltage, and any other gate circuit is constituted by a transistor having a high threshold voltage. Consequently, the gate circuit on the critical path can be operated at a high speed, and the overall leak electric current can be suppressed, thereby reducing the consumption power.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: June 15, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidemasa Zama, Masayuki Koizumi, Yukiko Ito, Kimiyoshi Usami, Naoyuki Kawabe, Masahiro Kanazawa, Toshiyuki Furusawa
  • Publication number: 20040021485
    Abstract: A semiconductor integrated circuit is disclosed, which comprises a tree structure of buffer circuit groups configured to have an enable-signal-controlled AND buffer circuit at least in a final stage, a latch circuit provided in a correspondence to the enable-signal-controlled AND buffer circuit and configured to receive an enable signal and clock signal and deliver an output to an input portion of a final stage buffer circuit, an enable-signal-controlled AND buffer circuit provided in a portion of an intermediate stage of the buffer circuit groups, and an OR circuit provided in a correspondence to the intermediate stage enable-signal-controlled AND buffer circuit and configured to take a logical sum of a plurality of enable signals for controlling the operations of a plurality of enable-signal-controlled AND buffer circuits more on a load circuit side and deliver a logical sum output to an input portion of the intermediate stage enable-signal-controlled AND buffer circuit.
    Type: Application
    Filed: May 5, 2003
    Publication date: February 5, 2004
    Inventor: Masahiro Kanazawa
  • Patent number: 6683336
    Abstract: A semiconductor integrated circuit, a supply method of supplying multiple supply voltages therefor, and a record medium for storing a program of the supply method for supplying multiple voltages therefor in which a first cell to which multiple supply voltages are supplied is extracted (Step S1), the extracted cells are divided into groups (Step S2), cells for voltage supply are added and arranged according to the number of the groups (Step S3), and the cell for the voltage supply are connected to the first cell for supplying the plurality of voltages through a net for a power source supply (Step S4).
    Type: Grant
    Filed: July 3, 2000
    Date of Patent: January 27, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mutsunori Igarashi, Hiroshi Tanaka, Kimiyoshi Usami, Takashi Ishikawa, Masahiro Kanazawa, Chiharu Mizuno
  • Patent number: 6586982
    Abstract: A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: July 1, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Furusawa, Daisuke Sonoda, Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Hidemasa Zama, Masahiro Kanazawa