Abstract: A wiring board includes a first insulating layer, a pad formed on one surface of the first insulating layer, a second insulating layer, formed on the one surface of the first insulating layer, and including an opening exposing the pad, and a reinforcing metal layer formed in contact with the first insulating layer, and provided around the pad so as to be separated from the pad in a plan view. The pad is disposed inside the opening without making contact with the second insulating layer. An end, on a side of the first insulating layer, in a portion of an inner side surface of the opening of the second insulating layer makes contact with the reinforcing metal layer, and an end in another portion of the inner side surface of the opening of the second insulating layer makes contact with the one surface of the first insulating layer.

Abstract: A wiring substrate includes a first insulation layer, an electronic component including a first surface and a second surface which is an opposite surface to the first surface, the electronic component being mounted on the first insulation layer with the first surface facing toward the first insulation layer, and a second insulation layer including a first layer and a second layer. The first layer is formed on the first insulation layer and configured to cover the second surface of the electronic component, and the second layer is stacked on the first layer. The first layer includes therein fillers. At least one of the fillers is in direct contact with the second surface of the electronic component at one side, and is exposed from the first layer and is thus in direct contact with the second layer at the other side.

Abstract: A wiring substrate includes a first insulation layer, an electronic component including a first surface and a second surface which is an opposite surface to the first surface, the electronic component being mounted on the first insulation layer with the first surface facing toward the first insulation layer, and a second insulation layer including a first layer and a second layer. The first layer is formed on the first insulation layer and configured to cover the second surface of the electronic component, and the second layer is stacked on the first layer. The first layer includes therein fillers. At least one of the fillers is in direct contact with the second surface of the electronic component at one side, and is exposed from the first layer and is thus in direct contact with the second layer at the other side.

Abstract: An electronic component device includes a first coreless wiring substrate, an electronic component mounted on the first coreless wiring substrate, a second coreless wiring substrate disposed above the first coreless wiring substrate and the electronic component such that the second coreless wiring substrate is spaced from the first coreless wiring substrate and the electronic component, a connection terminal that connects the first coreless wiring substrate and the second coreless wiring substrate, and a sealing resin filled between the first and second coreless wiring substrates. Each of the first and second coreless wiring substrates include an insulating layer, a wiring layer, and a reinforcing layer embedded in the insulating layer and provided in a region overlaying the electronic component.

Abstract: An electronic component device includes a cored wiring substrate, an electronic component, a reinforcing layer, a connection terminal, and sealing resin. The cored wiring substrate includes a core layer. The electronic component is mounted on the cored wiring substrate. The coreless wiring substrate is disposed on the cored wiring substrate and the electronic component. The reinforcing layer is provided in the coreless wiring substrate and in a region corresponding to the electronic component. The connection terminal connects the cored wiring substrate and the coreless wiring substrate. The sealing resin is filled between the cored wiring substrate and the coreless wiring substrate.

Abstract: A wiring board, includes a core substrate that includes first pads for mounting a semiconductor chip, second pads provided at the periphery of the first pads, and a solder resist layer that selectively exposes the first pads and the second pads; a first insulation layer, formed on the solder resist layer, including an opening to be formed in a frame shape such that to expose the first pads and cover the second pads; and external connection terminals penetrating the first insulation layer to be electrically connected to the second pads, respectively, and partially exposed from the first insulation layer, wherein the core substrate includes a second insulation layer, wherein the first pads, the second pads and the solder resist layer are directly formed on the second insulation layer, and wherein a rim of an inner wall surface of the opening at the core substrate side contacts the solder resist layer.

Abstract: An electronic component device includes a cored wiring substrate, an electronic component, a reinforcing layer, a connection terminal, and sealing resin. The cored wiring substrate includes a core layer. The electronic component is mounted on the cored wiring substrate. The coreless wiring substrate is disposed on the cored wiring substrate and the electronic component. The reinforcing layer is provided in the coreless wiring substrate and in a region corresponding to the electronic component. The connection terminal connects the cored wiring substrate and the coreless wiring substrate. The sealing resin is filled between the cored wiring substrate and the coreless wiring substrate.

Abstract: An electronic component device includes: a lower wiring substrate; an electronic component on the lower wiring substrate; an upper wiring substrate disposed above the lower wiring substrate and the electronic component; a bump conductor disposed between the lower wiring substrate and the upper wiring substrate to electrically connect the lower wiring substrate and the upper wiring substrate; and a sealing resin provided between the lower wiring substrate and the upper wiring substrate to seal the electronic component and the bump conductor. The upper wiring substrate includes: a first wiring layer directly connected to the bump conductor; and a first insulating layer having an opening portion through which the first wiring layer is exposed and disposed to cover the first wiring layer. The first wiring layer and the first insulating layer are not opposed to the electronic component in a thickness direction of the electronic component device.

Abstract: An electronic component device includes: a lower wiring substrate; an electronic component on the lower wiring substrate; an upper wiring substrate disposed above the lower wiring substrate and the electronic component; a bump conductor disposed between the lower wiring substrate and the upper wiring substrate to electrically connect the lower wiring substrate and the upper wiring substrate; and a sealing resin provided between the lower wiring substrate and the upper wiring substrate to seal the electronic component and the bump conductor. The upper wiring substrate includes: a first wiring layer directly connected to the bump conductor; and a first insulating layer having an opening portion through which the first wiring layer is exposed and disposed to cover the first wiring layer. The first wiring layer and the first insulating layer are not opposed to the electronic component in a thickness direction of the electronic component device.

Abstract: According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

Abstract: An electronic component device includes a cored wiring substrate, an electronic component, a reinforcing layer, a connection terminal, and sealing resin. The cored wiring substrate includes a core layer. The electronic component is mounted on the cored wiring substrate. The coreless wiring substrate is disposed on the cored wiring substrate and the electronic component. The reinforcing layer is provided in the coreless wiring substrate and in a region corresponding to the electronic component. The connection terminal connects the cored wiring substrate and the coreless wiring substrate. The sealing resin is filled between the cored wiring substrate and the coreless wiring substrate.

Abstract: A semiconductor package includes a semiconductor chip including a circuit forming surface and a side surface, and a sealing insulation layer that seals the circuit forming surface and the side surface of the semiconductor chip, the sealing insulation layer having a first surface on a side of the circuit forming surface. At least one wiring layer and at least one insulation layer are formed one on top of the other on the first surface. The wiring layer formed on the first surface is electrically connected to the semiconductor chip. The insulation layer has a reinforcement member installed therein.

Abstract: A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the outer edge of the upper surface of the core substrate. A second insulating layer fills the openings of the metal plate and the conductive layer and covers the outer edge of the lower surface of the core substrate, the conductive layer, and the semiconductor chip. The metal plate is thinner than the semiconductor chip. Total thickness of the conductive layer and the core substrate is equal to or larger than the thickness of the semiconductor chip.

Abstract: A wiring board has a structure where multiple wiring layers are stacked one on top of another with insulating layers interposed therebetween. A sheet-shaped member is buried in an outermost insulating layer located on a side of the structure opposite to a side on which a semiconductor element is to be mounted. The sheet-shaped member has a modulus of elasticity and a coefficient of thermal expansion which are similar to a modulus of elasticity and a coefficient of thermal expansion of the semiconductor element. The sheet-shaped member is made of a material having a modulus of elasticity and a coefficient of thermal expansion which are enough to bring respective distributions thereof into a substantially symmetric form in a direction orthogonal to a surface of the wiring board in the case where the semiconductor element is mounted.

Abstract: A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.

Abstract: A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the outer edge of the upper surface of the core substrate. A second insulating layer fills the openings of the metal plate and the conductive layer and covers the outer edge of the lower surface of the core substrate, the conductive layer, and the semiconductor chip. The metal plate is thinner than the semiconductor chip. Total thickness of the conductive layer and the core substrate is equal to or larger than the thickness of the semiconductor chip.

Abstract: A semiconductor package includes a semiconductor chip including a circuit forming surface and a side surface, and a sealing insulation layer that seals the circuit forming surface and the side surface of the semiconductor chip, the sealing insulation layer having a first surface on a side of the circuit forming surface. At least one wiring layer and at least one insulation layer are formed one on top of the other on the first surface. The wiring layer formed on the first surface is electrically connected to the semiconductor chip. The insulation layer has a reinforcement member installed therein.

Abstract: According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

Abstract: A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.

Abstract: A wiring board has a structure where multiple wiring layers are stacked one on top of another with insulating layers interposed therebetween. A sheet-shaped member is buried in an outermost insulating layer located on a side of the structure opposite to a side on which a semiconductor element is to be mounted. The sheet-shaped member has a modulus of elasticity and a coefficient of thermal expansion which are similar to a modulus of elasticity and a coefficient of thermal expansion of the semiconductor element. The sheet-shaped member is made of a material having a modulus of elasticity and a coefficient of thermal expansion which are enough to bring respective distributions thereof into a substantially symmetric form in a direction orthogonal to a surface of the wiring board in the case where the semiconductor element is mounted.