Patents by Inventor Masahiro Nagasu

Masahiro Nagasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6204717
    Abstract: A semiconductor circuit or a semiconductor device has the current-voltage characteristic that, in a blocking-state of the semiconductor circuit or the semiconductor device, a current gently flows for values of a voltage equal to or greater than a first voltage value but equal to or smaller than a second voltage, whereas a current abruptly flows for values of a voltage greater than the second voltage value. Due to the current-voltage characteristic, energy accumulated in an inductance provided within the circuit is consumed by a differential resistance of the semiconductor circuit or a semiconductor, thereby prevent the occurrence of the electromagnetic noise and the excessively large voltage.
    Type: Grant
    Filed: May 21, 1996
    Date of Patent: March 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Nagasu, Hideo Kobayashi, Hideki Miyazaki, Shin Kimura, Junichi Sakano, Mutsuhiro Mori
  • Patent number: 5962877
    Abstract: An inverter with an improved semiconductor device is provided having a pn junction composed of a first semiconductor layer made of a first conductivity type semiconductor and a second semiconductor layer made of a second conductivity type semiconductor having a wider band-gap than that of the first semiconductor layer.
    Type: Grant
    Filed: July 1, 1997
    Date of Patent: October 5, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Sakurai, Masahiro Nagasu
  • Patent number: 5877518
    Abstract: A semiconductor switching device is provided having a pn junction composed of a first semiconductor layer made of a first conductivity type semiconductor and a second semiconductor layer made of a second conductivity type semiconductor having a wider band-gap than that of the first semiconductor layer.
    Type: Grant
    Filed: July 20, 1995
    Date of Patent: March 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Sakurai, Masahiro Nagasu
  • Patent number: 5859446
    Abstract: In a diode, the backward length L of an anode electrode in a region, where a semiconductor layer of a p.sup.+ conductivity type and an anode electrode do not contact each other, is made longer than the diffusion length of holes in a semiconductor layer of an n.sup.- conductivity type for obtaining a large critical di/dt.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: January 12, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Nagasu, Mutsuhiro Mori, Hideo Kobayashi, Junichi Sakano
  • Patent number: 5831293
    Abstract: There is provided a semiconductor substrate which includes a pair of main surfaces, a first semiconductor layer of a first conductivity type adjacent to one of the main surface, a second semiconductor layer of a second conducting type of which impurity concentration is lower than that of the first semiconductor layer and which is adjacent to the first semiconductivity, a third semiconductor layer of the first conductivity type adjacent to the second semiconductor, and a fourth semiconductor of the second conductivity type of which impurity concentration is higher than that of the third semiconductor and which is adjacent to the other of the main surfaces and the third semiconductor.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: November 3, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuo Mizoguchi, Masahiro Nagasu, Hideo Kobayashi, Tsutomu Yatsuo
  • Patent number: 5767555
    Abstract: A compound semiconductor device including a MISFET and a thyristor connected in series wherein either the withstanding voltage between the MISFET p base layer and the thyristor p base layer is set lower than the withstanding voltage of the MISFET, the MISFET is turned off under a condition that the MISFET p base layer and the thyristor p base layer are connected via a p channel or the lateral resistance of the thyristor p base layer is reduced, thereby the safe operating region of the compound semiconductor device is extended.
    Type: Grant
    Filed: March 7, 1996
    Date of Patent: June 16, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Sakano, Hideo Kobayashi, Masahiro Nagasu, Mutsuhiro Mori