Abstract: [Problem] In a case where a risk of accumulating deposits on an EGR valve is low, the EGR valve is controlled to be opened as much as possible, and accordingly, emission of NOx contained in exhaust gas to external environment is reduced as much as possible. [Solution] An engine includes a control unit that controls the EGR valve. The control unit selects a predetermined control mode from at least a first mode, a second mode, and a third mode according to at least an engine speed and a fuel injection amount, and controls the EGR valve in the selected control mode. The first mode is a control mode in which the EGR valve is fully closed. The second mode is a control mode in which the opening degree of the EGR valve is adjusted according to the operation state of the engine. The third mode is a control mode in which an ON period in which the opening degree of the EGR valve is adjusted according to the operation state of the engine and an OFF period in which the EGR valve is fully closed are repeated.

Abstract: Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks B0 to B3 in a sector, in which a block address BA for selecting one of blocks B0 to B3 is held in block address buffer (BAB) 3. Holding operation is executed prior to reading or writing operation, and hence in subsequent reading operation or writing operation, re-input is not needed. Depending on the held block address BA, any one of selection signals YDn (n=0 to 3) is selected, and any one block is selected depending on the selection signal YDn. This state is maintained until the block address BA held in the block address buffer (BAB) 3 is rewritten, and therefore it is not required to enter or decode the block address BA on every occasion of reading and/or writing operation, so that the access operation can be executed promptly and at low current consumption.

Abstract: A communication apparatus for receiving maintenance data required for maintaining a device to be maintained and supplying maintenance data to the device to be maintained, and method are provided. The communication apparatus includes an acquisition unit for acquiring identification information for identifying the device and a sending unit for sending identification information acquired by the acquisition unit. The apparatus includes a receiving unit for receiving maintenance data including the identification information sent by the sending unit and a supply unit for supplying said maintenance data received by said receiving unit to said device to be maintained.

Abstract: Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks B0 to B3 in a sector, in which a block address BA for selecting one of blocks B0 to B3 is held in block address buffer (BAB) 3. Holding operation is executed prior to reading or writing operation, and hence in subsequent reading operation or writing operation, re-input is not needed. Depending on the held block address BA, any one of selection signals YDn (n=0 to 3) is selected, and any one block is selected depending on the selection signal YDn. This state is maintained until the block address BA held in the block address buffer (BAB) 3 is rewritten, and therefore it is not required to enter or decode the block address BA on every occasion of reading and/or writing operation, so that the access operation can be executed promptly and at low current consumption.

Abstract: A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.

Abstract: A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line.

Abstract: A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.

Abstract: A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.

Abstract: A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line.

Abstract: A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal.

Abstract: A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.

Abstract: A nonvolatile storage including a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased; a write amplifier for writing the erase setting information in the volatile memory cell array; a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of the erasing operation; and a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of readout operation.

Abstract: A communication apparatus for receiving maintenance data required for maintaining a device to be maintained and supplying maintenance data to the device to be maintained, and method are provided. The communication apparatus includes an acquisition unit for acquiring identification information for identifying the device and a sending unit for sending identification information acquired by the acquisition unit. The apparatus includes a receiving unit for receiving maintenance data including the identification information sent by the sending unit and a supply unit for supplying said maintenance data received by said receiving unit to said device to be maintained.

Abstract: A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.

Abstract: A nonvolatile storage is disclosed which has a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased; a write amplifier for writing the erase setting information in the volatile memory cell array; a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of the erasing operation; and a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of readout operation.

Abstract: Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks B0 to B3 in a sector, in which a block address BA for selecting one of blocks B0 to B3 is held in block address buffer (BAB) 3. Holding operation is executed prior to reading or writing operation, and hence in subsequent reading operation or writing operation, re-input is not needed. Depending on the held block address BA, any one of selection signals YDn (n=0 to 3) is selected, and any one block is selected depending on the selection signal YDn. This state is maintained until the block address BA held in the block address buffer (BAB) 3 is rewritten, and therefore it is not required to enter or decode the block address BA on every occasion of reading and/or writing operation, so that the access operation can be executed promptly and at low current consumption.

Abstract: Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.

Abstract: Upon receiving a level of a second node through a third switch in the first half of a first period, a holding circuit outputs it as a fuse signal indicating a blown-out state of a fuse. Since the third switch turns off in the second half of the first period, a change in level of the second node occurring thereafter will not affect data in the holding circuit, whereby prevents malfunction of a fuse circuit. With the fuse blown, a level of a first node gets fixed at that of a second power supply line after the first period. This eliminates a voltage difference between both ends of the fuse, thereby preventing a growback. No occurrence of growback makes just one fuse blowing sufficient for the fuse circuit even with the fuse not completely cut off. This consequently shortens a time for blowing the fuse in a test process.

Abstract: A semiconductor memory device that performs a flash write operation without increasing the circuit area. Column selection lines CL0-CL7 extend parallel to word lines at locations corresponding to where column gates are formed. During a flash write mode, the subcolumn decoder 14 simultaneously selects the column selection lines. This writes cell information to every memory cell connected to the selected word line.

Abstract: According to an aspect of the present invention, a memory device having a plurality of banks carries out bank interleaving by use of a plurality of common data buses, the number of which is less than the number of the banks. The present invention enables the data to be read more rapidly while suppressing the increase of the chip area.