Patents by Inventor Masahiro Shibata

Masahiro Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250008219
    Abstract: A shake amount acquisition apparatus includes a first acquisition unit configured to acquire a shake detection result from a shake detection unit that is configured to detect a shake and is provided in a rotation portion driven to rotate with respect to a base, a second acquisition unit configured to acquire a drive velocity of the rotation portion, and a reference value calculation unit configured to calculate a reference value of the shake detection unit based on the shake detection result and the drive velocity.
    Type: Application
    Filed: June 27, 2024
    Publication date: January 2, 2025
    Inventor: MASAHIRO SHIBATA
  • Publication number: 20240347494
    Abstract: A semiconductor device includes a semiconductor substrate; at least one transistor located on the semiconductor substrate and including a plurality of semiconductor layers; an electrode provided for the transistor; an organic insulating film having an opening in a region overlapping the transistor and the electrode in plan view in a first direction perpendicular to the semiconductor substrate; and a bump located over the at least one transistor in plan view in the first direction and electrically connected to the electrode through the opening of the organic insulating film. The width of the bump in a second direction parallel to the semiconductor substrate is smaller than the width of the opening of the organic insulating film in the second direction.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mari SAJI, Atsushi KUROKAWA, Masahiro SHIBATA
  • Publication number: 20240339425
    Abstract: A semiconductor device includes a semiconductor substrate, at least one transistor on the semiconductor substrate and including semiconductor layers, a wiring on the transistor, a first insulating film including a first opening in a region overlapping the transistor and the wiring in plan view in a first direction perpendicular to the semiconductor substrate, a first redistribution layer on the first insulating film, overlapping the at least one transistor in the first direction in plan view, and electrically connected to the wiring via the first opening, a second insulating film covering the first redistribution layer and the first insulating film and provided with a second opening in a region overlapping at least a part of the first redistribution layer in the first direction in plan view, and a bump electrically connected to the first redistribution layer via the second opening.
    Type: Application
    Filed: June 21, 2024
    Publication date: October 10, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mari SAJI, Atsushi KUROKAWA, Masahiro SHIBATA
  • Publication number: 20240280763
    Abstract: An optical connector in one embodiment includes an optical fiber, a ferrule assembly, and a housing. The housing has a positioning part defining an accommodation position of the ferrule assembly. The positioning part has an inclined surface with which a part of the ferrule assembly is to contact and the ferrule assembly includes a ferrule, a sleeve, and a flange. The sleeve includes a projection and the flange is disposed between the positioning part and the projection of the sleeve, and has a flange front surface including an edge contacting the inclined surface of the positioning part and a flange rear surface contacting or being close to the projection of the sleeve.
    Type: Application
    Filed: June 9, 2022
    Publication date: August 22, 2024
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC OPTIFRONTIER CO., LTD.
    Inventors: Yuki ARAO, Tetsu MORISHIMA, Masahiro SHIBATA
  • Publication number: 20240272374
    Abstract: An optical connector of one embodiment includes an optical fiber, a ferrule assembly, and a housing provided with a positioning part on an inner wall surface for suppressing a fluctuation in an aligning state of the optical fiber with respect to the housing. The positioning part includes an inclined surface and a facing surface which contact a part of the ferrule assembly. The ferrule assembly includes a ferrule, and a sleeve member. The sleeve member is constituted by a sleeve and a flange which has edges contacting the inclined surface and the facing surface respectively. Of an outer peripheral portion of the flange, a portion including the edges facing at least one of the inclined surface and the facing surface includes a set including a deformation absorbing part and two contact portions disposed on both sides of the deformation absorbing part.
    Type: Application
    Filed: June 9, 2022
    Publication date: August 15, 2024
    Applicants: SUMITOMO ELECTRIC INDUSTRIES., LTD., SUMITOMO ELECTRIC OPTIFRONTIER CO., LTD.
    Inventors: Yuki ARAO, Tetsu MORISHIMA, Masahiro SHIBATA
  • Publication number: 20240153704
    Abstract: A capacitor including a lower layer electrode, a dielectric film, and an upper layer electrode sequentially laminated on a partial area of an upper surface serving as one surface of a substrate formed from a compound semiconductor from a side closest to the substrate is disposed. A coating formed from an insulating metal oxide or a silicon oxide is disposed on or above the dielectric film. When the upper surface is viewed in a plan, the coating extends throughout an edge of the lower layer electrode from an area inside the edge of the lower layer electrode to an area outside the edge.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 9, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Hiroaki TOKUYA, Masayuki AOIKE, Masahiro SHIBATA
  • Patent number: 11978786
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: May 7, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Patent number: 11948986
    Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: April 2, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Masahiro Shibata, Hiroaki Tokuya, Mari Saji
  • Publication number: 20230288643
    Abstract: An optical wiring includes a plurality of first set groups each including a plurality of first connecting components, a plurality of second set groups each including a plurality of second connecting components, and a receptacle which has a first end face and a second end face on an opposite side of the first end face. The first set groups are connected to the first end face side and the second set groups are connected to the second end face side. The first set groups faces the second set groups through the receptacle such that a direction in which the first connecting components are arranged and a direction in which the second connecting components are arranged are perpendicular to each other, and each of the first connecting components is optically connected to a corresponding one of the second connecting components in the receptacle.
    Type: Application
    Filed: September 13, 2021
    Publication date: September 14, 2023
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC OPTIFRONTIER CO., LTD.
    Inventors: Tetsuya NAKANISHI, Masahiro SHIBATA, Atsushi KATAOKA
  • Patent number: 11652016
    Abstract: A first layer conductor film is connected to an operation electrode through an opening in a first layer interlayer insulating film. An opening in a second layer interlayer insulating film is encompassed by the first layer conductor film in plan view. A second layer conductor film is connected to the first layer conductor film through the opening in a second layer interlayer insulating film. The average, along a first direction, of distances in a second direction, which is perpendicular to the first direction, from the opening in the first layer interlayer insulating film to the side surface of the opening in the second layer interlayer insulating film is greater than or equal to a distance in a height direction from an upper opening plane of the opening in the first layer interlayer insulating film to a lower opening plane of the opening in the second layer interlayer insulating film.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: May 16, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mari Saji, Masahiro Shibata, Atsushi Kurokawa
  • Patent number: 11626511
    Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 11, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Patent number: 11621678
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: April 4, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura
  • Patent number: 11502016
    Abstract: A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 15, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Masahiro Shibata
  • Patent number: 11469187
    Abstract: At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: October 11, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroaki Tokuya, Masahiro Shibata, Akihiko Ozaki, Satoshi Goto, Fumio Harima, Atsushi Kurokawa
  • Patent number: 11363204
    Abstract: An image processing apparatus that corrects image blurring with respect to image data that has been captured using a lens that forms a subject image which has been compressed in at least one of first and second directions that are orthogonal to an optical axis is disclosed. The apparatus applies geometric transformation processing to the image data based on first information related to a compression ratio of a subject image applied by the lens and on second information related to a rotation angle of the device motion. The geometric transformation processing includes correction processing for rotation transformation of the subject image attributed to the device motion around the optical axis, and shearing processing.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: June 14, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Masahiro Shibata
  • Publication number: 20220029004
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Application
    Filed: October 6, 2021
    Publication date: January 27, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Shigeki KOYA, Masao KONDO, Takayuki TSUTSUI
  • Publication number: 20210391429
    Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 16, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi KUROKAWA, Masahiro SHIBATA, Hiroaki TOKUYA, Mari SAJI
  • Publication number: 20210391233
    Abstract: A first layer conductor film is connected to an operation electrode through an opening in a first layer interlayer insulating film. An opening in a second layer interlayer insulating film is encompassed by the first layer conductor film in plan view. A second layer conductor film is connected to the first layer conductor film through the opening in a second layer interlayer insulating film. The average, along a first direction, of distances in a second direction, which is perpendicular to the first direction, from the opening in the first layer interlayer insulating film to the side surface of the opening in the second layer interlayer insulating film is greater than or equal to a distance in a height direction from an upper opening plane of the opening in the first layer interlayer insulating film to a lower opening plane of the opening in the second layer interlayer insulating film.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 16, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mari SAJI, Masahiro SHIBATA, Atsushi KUROKAWA
  • Patent number: D1036389
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: July 23, 2024
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC OPTIFRONTIER CO., LTD.
    Inventors: Dai Sasaki, Masahiro Shibata
  • Patent number: D1038038
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: August 6, 2024
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC OPTIFRONTIER CO., LTD.
    Inventors: Dai Sasaki, Masahiro Shibata