Patents by Inventor Masahiro Shibata
Masahiro Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240151919Abstract: This optical device includes at least one magnetic element including a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, a laser diode, and a waveguide, in which the waveguide includes at least one input waveguide optically connected to the laser diode and an output waveguide connected to the input waveguide, and at least some of light propagating in at least one of the input waveguide and the output waveguide is applied to the magnetic element.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Applicant: TDK CORPORATIONInventors: Tetsuya SHIBATA, Hideaki FUKUZAWA, Tomohito MIZUNO, Masahiro SHINKAI
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Publication number: 20240153704Abstract: A capacitor including a lower layer electrode, a dielectric film, and an upper layer electrode sequentially laminated on a partial area of an upper surface serving as one surface of a substrate formed from a compound semiconductor from a side closest to the substrate is disposed. A coating formed from an insulating metal oxide or a silicon oxide is disposed on or above the dielectric film. When the upper surface is viewed in a plan, the coating extends throughout an edge of the lower layer electrode from an area inside the edge of the lower layer electrode to an area outside the edge.Type: ApplicationFiled: November 7, 2023Publication date: May 9, 2024Applicant: Murata Manufacturing Co., Ltd.Inventors: Hiroaki TOKUYA, Masayuki AOIKE, Masahiro SHIBATA
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Patent number: 11978786Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.Type: GrantFiled: October 6, 2021Date of Patent: May 7, 2024Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
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Patent number: 11953742Abstract: This optical device includes at least one magnetic element including a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, a laser diode, and a waveguide, in which the waveguide includes at least one input waveguide optically connected to the laser diode and an output waveguide connected to the input waveguide, and at least some of light propagating in at least one of the input waveguide and the output waveguide is applied to the magnetic element.Type: GrantFiled: March 14, 2022Date of Patent: April 9, 2024Assignee: TDK CORPORATIONInventors: Tetsuya Shibata, Hideaki Fukuzawa, Tomohito Mizuno, Masahiro Shinkai
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Patent number: 11948986Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.Type: GrantFiled: June 16, 2021Date of Patent: April 2, 2024Assignee: Murata Manufacturing Co., Ltd.Inventors: Atsushi Kurokawa, Masahiro Shibata, Hiroaki Tokuya, Mari Saji
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Publication number: 20230288643Abstract: An optical wiring includes a plurality of first set groups each including a plurality of first connecting components, a plurality of second set groups each including a plurality of second connecting components, and a receptacle which has a first end face and a second end face on an opposite side of the first end face. The first set groups are connected to the first end face side and the second set groups are connected to the second end face side. The first set groups faces the second set groups through the receptacle such that a direction in which the first connecting components are arranged and a direction in which the second connecting components are arranged are perpendicular to each other, and each of the first connecting components is optically connected to a corresponding one of the second connecting components in the receptacle.Type: ApplicationFiled: September 13, 2021Publication date: September 14, 2023Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC OPTIFRONTIER CO., LTD.Inventors: Tetsuya NAKANISHI, Masahiro SHIBATA, Atsushi KATAOKA
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Patent number: 11652016Abstract: A first layer conductor film is connected to an operation electrode through an opening in a first layer interlayer insulating film. An opening in a second layer interlayer insulating film is encompassed by the first layer conductor film in plan view. A second layer conductor film is connected to the first layer conductor film through the opening in a second layer interlayer insulating film. The average, along a first direction, of distances in a second direction, which is perpendicular to the first direction, from the opening in the first layer interlayer insulating film to the side surface of the opening in the second layer interlayer insulating film is greater than or equal to a distance in a height direction from an upper opening plane of the opening in the first layer interlayer insulating film to a lower opening plane of the opening in the second layer interlayer insulating film.Type: GrantFiled: June 11, 2021Date of Patent: May 16, 2023Assignee: Murata Manufacturing Co., Ltd.Inventors: Mari Saji, Masahiro Shibata, Atsushi Kurokawa
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Patent number: 11626511Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.Type: GrantFiled: November 30, 2018Date of Patent: April 11, 2023Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
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Patent number: 11621678Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.Type: GrantFiled: January 7, 2021Date of Patent: April 4, 2023Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura
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Patent number: 11502016Abstract: A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.Type: GrantFiled: October 27, 2020Date of Patent: November 15, 2022Assignee: Murata Manufacturing Co., Ltd.Inventors: Masao Kondo, Masahiro Shibata
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Patent number: 11469187Abstract: At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.Type: GrantFiled: July 30, 2020Date of Patent: October 11, 2022Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiroaki Tokuya, Masahiro Shibata, Akihiko Ozaki, Satoshi Goto, Fumio Harima, Atsushi Kurokawa
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Patent number: 11363204Abstract: An image processing apparatus that corrects image blurring with respect to image data that has been captured using a lens that forms a subject image which has been compressed in at least one of first and second directions that are orthogonal to an optical axis is disclosed. The apparatus applies geometric transformation processing to the image data based on first information related to a compression ratio of a subject image applied by the lens and on second information related to a rotation angle of the device motion. The geometric transformation processing includes correction processing for rotation transformation of the subject image attributed to the device motion around the optical axis, and shearing processing.Type: GrantFiled: March 15, 2021Date of Patent: June 14, 2022Assignee: CANON KABUSHIKI KAISHAInventor: Masahiro Shibata
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Publication number: 20220029004Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.Type: ApplicationFiled: October 6, 2021Publication date: January 27, 2022Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Shigeki KOYA, Masao KONDO, Takayuki TSUTSUI
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Publication number: 20210391233Abstract: A first layer conductor film is connected to an operation electrode through an opening in a first layer interlayer insulating film. An opening in a second layer interlayer insulating film is encompassed by the first layer conductor film in plan view. A second layer conductor film is connected to the first layer conductor film through the opening in a second layer interlayer insulating film. The average, along a first direction, of distances in a second direction, which is perpendicular to the first direction, from the opening in the first layer interlayer insulating film to the side surface of the opening in the second layer interlayer insulating film is greater than or equal to a distance in a height direction from an upper opening plane of the opening in the first layer interlayer insulating film to a lower opening plane of the opening in the second layer interlayer insulating film.Type: ApplicationFiled: June 11, 2021Publication date: December 16, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Mari SAJI, Masahiro SHIBATA, Atsushi KUROKAWA
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Publication number: 20210391429Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.Type: ApplicationFiled: June 16, 2021Publication date: December 16, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Atsushi KUROKAWA, Masahiro SHIBATA, Hiroaki TOKUYA, Mari SAJI
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Patent number: 11164963Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.Type: GrantFiled: April 21, 2020Date of Patent: November 2, 2021Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
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Patent number: 11158592Abstract: Transistors including semiconductor regions where operating current flows are provided above a substrate. Operating electrodes of conductive material having thermal conductivity higher than the semiconductor regions and contacting the semiconductor regions to conduct operating current to the semiconductor regions are disposed. A conductor pillar for external connection contains contact regions where the semiconductor regions and the operating electrodes contact, and is electrically connected to the operating electrodes. The contact regions are disposed in a first direction. Each contact region has a planar shape long in a second direction orthogonal to the first direction. A first average distance, obtained by averaging distances in the second direction from each end portion of the contact region in the second direction to an edge of the conductor pillar across the contact regions, exceeds an average distance value in a height direction from the contact region to a top surface of the conductor pillar.Type: GrantFiled: December 11, 2019Date of Patent: October 26, 2021Assignee: Murata Manufacturing Co., Ltd.Inventors: Masahiro Shibata, Atsushi Kurokawa
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Publication number: 20210297597Abstract: An image processing apparatus that corrects image blurring with respect to image data that has been captured using a lens that forms a subject image which has been compressed in at least one of first and second directions that are orthogonal to an optical axis is disclosed. The apparatus applies geometric transformation processing to the image data based on first information related to a compression ratio of a subject image applied by the lens and on second information related to a rotation angle of the device motion. The geometric transformation processing includes correction processing for rotation transformation of the subject image attributed to the device motion around the optical axis, and shearing processing.Type: ApplicationFiled: March 15, 2021Publication date: September 23, 2021Inventor: Masahiro Shibata
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Publication number: 20210126591Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.Type: ApplicationFiled: January 7, 2021Publication date: April 29, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Kenichi NAGURA
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Patent number: 10957617Abstract: A semiconductor chip includes an active element on a first surface of a substrate. A heat-conductive film having a higher thermal conductivity than the substrate is disposed at a position different from a position of the active element. An insulating film covering the active element and heat-conductive film is disposed on the first surface. A bump electrically connected to the heat-conductive film is disposed on the insulating film. A via-hole extends from a second surface opposite to the first surface to the heat-conductive film. A heat-conductive member having a higher thermal conductivity than the substrate is continuously disposed from a region of the second surface overlapping the active element in plan view to an inner surface of the via-hole. The bump is connected to a land of a printed circuit board facing the first surface. The semiconductor chip is sealed with a resin.Type: GrantFiled: April 3, 2019Date of Patent: March 23, 2021Assignee: Murata Manufacturing Co., Ltd.Inventors: Masao Kondo, Isao Obu, Yasunari Umemoto, Yasuhisa Yamamoto, Masahiro Shibata, Takayuki Tsutsui