Patents by Inventor Masahiro Shibata

Masahiro Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210391429
    Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 16, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi KUROKAWA, Masahiro SHIBATA, Hiroaki TOKUYA, Mari SAJI
  • Publication number: 20210391233
    Abstract: A first layer conductor film is connected to an operation electrode through an opening in a first layer interlayer insulating film. An opening in a second layer interlayer insulating film is encompassed by the first layer conductor film in plan view. A second layer conductor film is connected to the first layer conductor film through the opening in a second layer interlayer insulating film. The average, along a first direction, of distances in a second direction, which is perpendicular to the first direction, from the opening in the first layer interlayer insulating film to the side surface of the opening in the second layer interlayer insulating film is greater than or equal to a distance in a height direction from an upper opening plane of the opening in the first layer interlayer insulating film to a lower opening plane of the opening in the second layer interlayer insulating film.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 16, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mari SAJI, Masahiro SHIBATA, Atsushi KUROKAWA
  • Patent number: 11164963
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: November 2, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Patent number: 11158592
    Abstract: Transistors including semiconductor regions where operating current flows are provided above a substrate. Operating electrodes of conductive material having thermal conductivity higher than the semiconductor regions and contacting the semiconductor regions to conduct operating current to the semiconductor regions are disposed. A conductor pillar for external connection contains contact regions where the semiconductor regions and the operating electrodes contact, and is electrically connected to the operating electrodes. The contact regions are disposed in a first direction. Each contact region has a planar shape long in a second direction orthogonal to the first direction. A first average distance, obtained by averaging distances in the second direction from each end portion of the contact region in the second direction to an edge of the conductor pillar across the contact regions, exceeds an average distance value in a height direction from the contact region to a top surface of the conductor pillar.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: October 26, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Shibata, Atsushi Kurokawa
  • Publication number: 20210297597
    Abstract: An image processing apparatus that corrects image blurring with respect to image data that has been captured using a lens that forms a subject image which has been compressed in at least one of first and second directions that are orthogonal to an optical axis is disclosed. The apparatus applies geometric transformation processing to the image data based on first information related to a compression ratio of a subject image applied by the lens and on second information related to a rotation angle of the device motion. The geometric transformation processing includes correction processing for rotation transformation of the subject image attributed to the device motion around the optical axis, and shearing processing.
    Type: Application
    Filed: March 15, 2021
    Publication date: September 23, 2021
    Inventor: Masahiro Shibata
  • Publication number: 20210126591
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Application
    Filed: January 7, 2021
    Publication date: April 29, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Kenichi NAGURA
  • Patent number: 10957617
    Abstract: A semiconductor chip includes an active element on a first surface of a substrate. A heat-conductive film having a higher thermal conductivity than the substrate is disposed at a position different from a position of the active element. An insulating film covering the active element and heat-conductive film is disposed on the first surface. A bump electrically connected to the heat-conductive film is disposed on the insulating film. A via-hole extends from a second surface opposite to the first surface to the heat-conductive film. A heat-conductive member having a higher thermal conductivity than the substrate is continuously disposed from a region of the second surface overlapping the active element in plan view to an inner surface of the via-hole. The bump is connected to a land of a printed circuit board facing the first surface. The semiconductor chip is sealed with a resin.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 23, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Isao Obu, Yasunari Umemoto, Yasuhisa Yamamoto, Masahiro Shibata, Takayuki Tsutsui
  • Publication number: 20210043535
    Abstract: A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.
    Type: Application
    Filed: October 27, 2020
    Publication date: February 11, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masao KONDO, Masahiro SHIBATA
  • Publication number: 20210035922
    Abstract: At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 4, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Hiroaki TOKUYA, Masahiro SHIBATA, Akihiko OZAKI, Satoshi GOTO, Fumio HARIMA, Atsushi KUROKAWA
  • Patent number: 10903803
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: January 26, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura
  • Patent number: 10847436
    Abstract: A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: November 24, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Masahiro Shibata
  • Publication number: 20200251579
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Shigeki KOYA, Masao KONDO, Takayuki TSUTSUI
  • Publication number: 20200194394
    Abstract: Transistors including semiconductor regions where operating current flows are provided above a substrate. Operating electrodes of conductive material having thermal conductivity higher than the semiconductor regions and contacting the semiconductor regions to conduct operating current to the semiconductor regions are disposed. A conductor pillar for external connection contains contact regions where the semiconductor regions and the operating electrodes contact, and is electrically connected to the operating electrodes. The contact regions are disposed in a first direction. Each contact region has a planar shape long in a second direction orthogonal to the first direction. A first average distance, obtained by averaging distances in the second direction from each end portion of the contact region in the second direction to an edge of the conductor pillar across the contact regions, exceeds an average distance value in a height direction from the contact region to a top surface of the conductor pillar.
    Type: Application
    Filed: December 11, 2019
    Publication date: June 18, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro SHIBATA, Atsushi KUROKAWA
  • Publication number: 20200177140
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Application
    Filed: February 7, 2020
    Publication date: June 4, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Kenichi NAGURA
  • Patent number: 10665704
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 26, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Patent number: 10665519
    Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 26, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata
  • Patent number: 10594271
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 17, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura
  • Patent number: 10570259
    Abstract: Provided is a composition capable of providing a formed article that, even when using continuous fibers, has excellent interfacial adhesion between the continuous fibers and a matrix resin, and as a result, has excellent mechanical strength (e.g., impact resistance and flexural strength). One aspect of a composition according to the present invention includes a polymer (A) including an amino group, fibers (B), and a thermoplastic resin (C), in which a content ratio of the fibers (B) is 70 parts by mass or more and 250 parts by mass or less based on 100 parts by mass of the thermoplastic resin (C). Another aspect of the composition according to the present invention includes a polymer (A) including an amino group, a non-woven fabric (B?), and a thermoplastic resin (C).
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: February 25, 2020
    Assignee: JSR CORPORATION
    Inventors: Shuugo Maeda, Masahiro Shibata, Akihiko Ookubo
  • Patent number: 10564370
    Abstract: A method for fabricating an optical connecting device with a holder having a through hole, multiple optical fibers, a guide member, and a resin body includes steps of: preparing optical-fiber parts to provide the multiple optical fibers; preparing first and second parts to provide the holder, the first and second parts having grooves for providing the through hole of the holder; fixing the parts providing the holder and the optical-fiber parts to each other to form a first product having the through hole produced from the grooves; providing an optical connector tool; positioning a component of the tool in the through hole of the first product to provide the guide member; and thereafter, fixing the component in the through hole with resin to form a second product in which the resin provides the resin body.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: February 18, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Mitsuharu Hirano, Akira Furuya, Koichi Koyama, Masahiro Shibata
  • Patent number: 10559547
    Abstract: A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: February 11, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Shibata, Daisuke Tokuda, Atsushi Kurokawa, Hiroaki Tokuya, Yasunari Umemoto