Patents by Inventor Masahiro Shibata

Masahiro Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12124096
    Abstract: This optical device includes at least one magnetic element including a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, a laser diode, and a waveguide, in which the waveguide includes at least one input waveguide optically connected to the laser diode and an output waveguide connected to the input waveguide, and at least some of light propagating in at least one of the input waveguide and the output waveguide is applied to the magnetic element.
    Type: Grant
    Filed: January 12, 2024
    Date of Patent: October 22, 2024
    Assignee: TDK CORPORATION
    Inventors: Tetsuya Shibata, Hideaki Fukuzawa, Tomohito Mizuno, Masahiro Shinkai
  • Publication number: 20240347494
    Abstract: A semiconductor device includes a semiconductor substrate; at least one transistor located on the semiconductor substrate and including a plurality of semiconductor layers; an electrode provided for the transistor; an organic insulating film having an opening in a region overlapping the transistor and the electrode in plan view in a first direction perpendicular to the semiconductor substrate; and a bump located over the at least one transistor in plan view in the first direction and electrically connected to the electrode through the opening of the organic insulating film. The width of the bump in a second direction parallel to the semiconductor substrate is smaller than the width of the opening of the organic insulating film in the second direction.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mari SAJI, Atsushi KUROKAWA, Masahiro SHIBATA
  • Publication number: 20240339425
    Abstract: A semiconductor device includes a semiconductor substrate, at least one transistor on the semiconductor substrate and including semiconductor layers, a wiring on the transistor, a first insulating film including a first opening in a region overlapping the transistor and the wiring in plan view in a first direction perpendicular to the semiconductor substrate, a first redistribution layer on the first insulating film, overlapping the at least one transistor in the first direction in plan view, and electrically connected to the wiring via the first opening, a second insulating film covering the first redistribution layer and the first insulating film and provided with a second opening in a region overlapping at least a part of the first redistribution layer in the first direction in plan view, and a bump electrically connected to the first redistribution layer via the second opening.
    Type: Application
    Filed: June 21, 2024
    Publication date: October 10, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mari SAJI, Atsushi KUROKAWA, Masahiro SHIBATA
  • Publication number: 20240323176
    Abstract: A client terminal (200) acquires a ticket (110) including a scope indicating an authorization condition, collects a context to indicate a state of the client terminal, sets the context in the ticket, and transmits the ticket. The authorization server (400) receives the ticket, determines a condition element other than the context among one or more condition elements indicated in the authorization condition as reinforcement information (111), requests the reinforcement information determined to a context reinforcement device (500), receives the reinforcement information, and verifies the scope based on the context and the reinforcement information.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takumi Mori, Masahiro FUJITA, Yoichi SHIBATA, Tadakazu YAMANAKA, Nori MATSUDA
  • Patent number: 12087762
    Abstract: Nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity above the substrate; a second nitride semiconductor layer of a second conductivity different from the first conductivity, above the first nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer; an electron transport layer and an electron supply layer disposed along inner surfaces of the first opening, in stated sequence from the substrate-side; a gate electrode above the electron supply layer, covering the first opening; a source electrode connected to the electron supply layer and the electron transport layer, at a position separated from the gate electrode; and a drain electrode on a surface of the substrate opposite to a surface on which the first nitride semiconductor layer is disposed. At least part of the second nitride semiconductor layer is fixed to a potential different from a potential of the source electrode.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: September 10, 2024
    Assignee: PANASONIC HOLDINGS CORPORATION
    Inventors: Daisuke Shibata, Satoshi Tamura, Masahiro Ogawa
  • Publication number: 20240280763
    Abstract: An optical connector in one embodiment includes an optical fiber, a ferrule assembly, and a housing. The housing has a positioning part defining an accommodation position of the ferrule assembly. The positioning part has an inclined surface with which a part of the ferrule assembly is to contact and the ferrule assembly includes a ferrule, a sleeve, and a flange. The sleeve includes a projection and the flange is disposed between the positioning part and the projection of the sleeve, and has a flange front surface including an edge contacting the inclined surface of the positioning part and a flange rear surface contacting or being close to the projection of the sleeve.
    Type: Application
    Filed: June 9, 2022
    Publication date: August 22, 2024
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC OPTIFRONTIER CO., LTD.
    Inventors: Yuki ARAO, Tetsu MORISHIMA, Masahiro SHIBATA
  • Publication number: 20240272374
    Abstract: An optical connector of one embodiment includes an optical fiber, a ferrule assembly, and a housing provided with a positioning part on an inner wall surface for suppressing a fluctuation in an aligning state of the optical fiber with respect to the housing. The positioning part includes an inclined surface and a facing surface which contact a part of the ferrule assembly. The ferrule assembly includes a ferrule, and a sleeve member. The sleeve member is constituted by a sleeve and a flange which has edges contacting the inclined surface and the facing surface respectively. Of an outer peripheral portion of the flange, a portion including the edges facing at least one of the inclined surface and the facing surface includes a set including a deformation absorbing part and two contact portions disposed on both sides of the deformation absorbing part.
    Type: Application
    Filed: June 9, 2022
    Publication date: August 15, 2024
    Applicants: SUMITOMO ELECTRIC INDUSTRIES., LTD., SUMITOMO ELECTRIC OPTIFRONTIER CO., LTD.
    Inventors: Yuki ARAO, Tetsu MORISHIMA, Masahiro SHIBATA
  • Publication number: 20240276084
    Abstract: A camera module includes, for example, a light source, a ToF sensor configured to detect reflected light from a subject that receives light from the light source, and a heat conduction member that conducts heat of the light source to the ToF sensor.
    Type: Application
    Filed: January 31, 2024
    Publication date: August 15, 2024
    Applicant: NIPPON CHEMI-CON CORPORATION
    Inventors: Katsuya TAMAKI, Masahiro KOMIYA, Naohisa SHIBATA
  • Publication number: 20240266431
    Abstract: A nitride semiconductor device includes: a substrate; an n-type drift layer; a p-type blocking layer; a gate opening which penetrates through the blocking layer to the drift layer; an electron transport layer and an electron supply layer provided on an inner face of the gate opening; a gate electrode above the electron supply layer and covering the gate opening; a source opening penetrating through the electron supply layer and the electron transport layer to the blocking layer; a source electrode covering the source opening, the source electrode being connected to the electron supply layer, the electron transport layer, and the blocking layer; and a drain electrode on a side of the substrate opposite from a side on which the blocking layer is located. A bottom face of the gate electrode is closer to the drain electrode than a bottom face of the blocking layer is.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 8, 2024
    Inventors: Daisuke SHIBATA, Satoshi TAMURA, Masahiro OGAWA
  • Patent number: 12046875
    Abstract: A quantum cascade laser device includes a semiconductor substrate, an active layer provided on the semiconductor substrate, and an upper clad layer provided on a side of the active layer opposite to the semiconductor substrate side and having a doping concentration of impurities of less than 1×1017 cm?3. Unit laminates included in the active layer each include a first emission upper level, a second emission upper level, and at least one emission lower level in their subband level structure. The active layer is configured to generate light having a center wavelength of 10 ?m or more due to electron transition between at least two levels of the first emission upper level, the second emission upper level, and the at least one emission lower level in the light emission layer in each of the unit laminates.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: July 23, 2024
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Kazuue Fujita, Masahiro Hitaka, Atsushi Sugiyama, Kousuke Shibata
  • Patent number: 12040695
    Abstract: A power conversion device includes a power conversion module, a phase change material, a heat dissipation member, a cooling mechanism, and a controller. A semiconductor switching element and a freewheeling diode configure a power conversion circuit. The phase change material is provided on a principal plane of a casing. The heat dissipation member includes a heat dissipation surface. The heat dissipation surface is overlapped with the principal plane to sandwich the phase change material. The cooling mechanism cools the heat dissipation member. The controller generates a driving signal for driving the power conversion circuit and controls the cooling mechanism. The controller includes a predetermined heating operation. The heating operation may drive the power conversion circuit, in a state that the cooling mechanism is stopped or intermittently operated, such that heat generation occurs in both the semiconductor switching element and the freewheeling diode.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 16, 2024
    Assignee: TMEIC CORPORATION
    Inventors: Naoya Shibata, Masahiro Kinoshita, Issei Fukasawa
  • Publication number: 20240153704
    Abstract: A capacitor including a lower layer electrode, a dielectric film, and an upper layer electrode sequentially laminated on a partial area of an upper surface serving as one surface of a substrate formed from a compound semiconductor from a side closest to the substrate is disposed. A coating formed from an insulating metal oxide or a silicon oxide is disposed on or above the dielectric film. When the upper surface is viewed in a plan, the coating extends throughout an edge of the lower layer electrode from an area inside the edge of the lower layer electrode to an area outside the edge.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 9, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Hiroaki TOKUYA, Masayuki AOIKE, Masahiro SHIBATA
  • Patent number: 11978786
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: May 7, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Patent number: 11948986
    Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: April 2, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Masahiro Shibata, Hiroaki Tokuya, Mari Saji
  • Publication number: 20230288643
    Abstract: An optical wiring includes a plurality of first set groups each including a plurality of first connecting components, a plurality of second set groups each including a plurality of second connecting components, and a receptacle which has a first end face and a second end face on an opposite side of the first end face. The first set groups are connected to the first end face side and the second set groups are connected to the second end face side. The first set groups faces the second set groups through the receptacle such that a direction in which the first connecting components are arranged and a direction in which the second connecting components are arranged are perpendicular to each other, and each of the first connecting components is optically connected to a corresponding one of the second connecting components in the receptacle.
    Type: Application
    Filed: September 13, 2021
    Publication date: September 14, 2023
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC OPTIFRONTIER CO., LTD.
    Inventors: Tetsuya NAKANISHI, Masahiro SHIBATA, Atsushi KATAOKA
  • Patent number: 11652016
    Abstract: A first layer conductor film is connected to an operation electrode through an opening in a first layer interlayer insulating film. An opening in a second layer interlayer insulating film is encompassed by the first layer conductor film in plan view. A second layer conductor film is connected to the first layer conductor film through the opening in a second layer interlayer insulating film. The average, along a first direction, of distances in a second direction, which is perpendicular to the first direction, from the opening in the first layer interlayer insulating film to the side surface of the opening in the second layer interlayer insulating film is greater than or equal to a distance in a height direction from an upper opening plane of the opening in the first layer interlayer insulating film to a lower opening plane of the opening in the second layer interlayer insulating film.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: May 16, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mari Saji, Masahiro Shibata, Atsushi Kurokawa
  • Patent number: 11626511
    Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 11, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Patent number: 11621678
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: April 4, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura
  • Patent number: D1036389
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: July 23, 2024
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC OPTIFRONTIER CO., LTD.
    Inventors: Dai Sasaki, Masahiro Shibata
  • Patent number: D1038038
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: August 6, 2024
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC OPTIFRONTIER CO., LTD.
    Inventors: Dai Sasaki, Masahiro Shibata