Patents by Inventor Masahiro Shibata
Masahiro Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10594271Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.Type: GrantFiled: June 7, 2019Date of Patent: March 17, 2020Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura
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Patent number: 10570259Abstract: Provided is a composition capable of providing a formed article that, even when using continuous fibers, has excellent interfacial adhesion between the continuous fibers and a matrix resin, and as a result, has excellent mechanical strength (e.g., impact resistance and flexural strength). One aspect of a composition according to the present invention includes a polymer (A) including an amino group, fibers (B), and a thermoplastic resin (C), in which a content ratio of the fibers (B) is 70 parts by mass or more and 250 parts by mass or less based on 100 parts by mass of the thermoplastic resin (C). Another aspect of the composition according to the present invention includes a polymer (A) including an amino group, a non-woven fabric (B?), and a thermoplastic resin (C).Type: GrantFiled: August 22, 2016Date of Patent: February 25, 2020Assignee: JSR CORPORATIONInventors: Shuugo Maeda, Masahiro Shibata, Akihiko Ookubo
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Patent number: 10564370Abstract: A method for fabricating an optical connecting device with a holder having a through hole, multiple optical fibers, a guide member, and a resin body includes steps of: preparing optical-fiber parts to provide the multiple optical fibers; preparing first and second parts to provide the holder, the first and second parts having grooves for providing the through hole of the holder; fixing the parts providing the holder and the optical-fiber parts to each other to form a first product having the through hole produced from the grooves; providing an optical connector tool; positioning a component of the tool in the through hole of the first product to provide the guide member; and thereafter, fixing the component in the through hole with resin to form a second product in which the resin provides the resin body.Type: GrantFiled: June 25, 2018Date of Patent: February 18, 2020Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Mitsuharu Hirano, Akira Furuya, Koichi Koyama, Masahiro Shibata
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Patent number: 10559547Abstract: A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface.Type: GrantFiled: June 12, 2018Date of Patent: February 11, 2020Assignee: Murata Manufacturing Co., Ltd.Inventors: Masahiro Shibata, Daisuke Tokuda, Atsushi Kurokawa, Hiroaki Tokuya, Yasunari Umemoto
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Publication number: 20200027805Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.Type: ApplicationFiled: September 30, 2019Publication date: January 23, 2020Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA
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Patent number: 10475717Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.Type: GrantFiled: February 19, 2018Date of Patent: November 12, 2019Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata
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Publication number: 20190326191Abstract: A semiconductor chip includes an active element on a first surface of a substrate. A heat-conductive film having a higher thermal conductivity than the substrate is disposed at a position different from a position of the active element. An insulating film covering the active element and heat-conductive film is disposed on the first surface. A bump electrically connected to the heat-conductive film is disposed on the insulating film. A via-hole extends from a second surface opposite to the first surface to the heat-conductive film. A heat-conductive member having a higher thermal conductivity than the substrate is continuously disposed from a region of the second surface overlapping the active element in plan view to an inner surface of the via-hole. The bump is connected to a land of a printed circuit board facing the first surface. The semiconductor chip is sealed with a resin.Type: ApplicationFiled: April 3, 2019Publication date: October 24, 2019Applicant: Murata Manufacturing Co., Ltd.Inventors: Masao KONDO, Isao OBU, Yasunari UMEMOTO, Yasuhisa YAMAMOTO, Masahiro SHIBATA, Takayuki TSUTSUI
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Patent number: 10442013Abstract: A cutting insert of an embodiment of the present invention includes an upper surface, a lower surface, a side surface connected to each of the upper surface and the lower surface, and an upper cutting edge located at an intersection of the upper surface and the side surface. The lower surface includes a mount part having alternately three first top portions spaced a distance a away from a central axis extending between the upper and lower surfaces and three second top portions spaced a distance b away from the central axis in a bottom view. The mount part further has a concave part including at least the central axis. The second top portions are located closer to the upper surface than the first top portions. A cutting tool with the cutting insert, and a method of manufacturing a machined product by using the cutting tool are also provided.Type: GrantFiled: August 21, 2017Date of Patent: October 15, 2019Assignee: KYOCERA CORPORATIONInventor: Masahiro Shibata
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Publication number: 20190296699Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.Type: ApplicationFiled: June 7, 2019Publication date: September 26, 2019Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Kenichi NAGURA
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Patent number: 10361666Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.Type: GrantFiled: April 5, 2018Date of Patent: July 23, 2019Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura
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Patent number: 10355114Abstract: An HBT includes a semiconductor substrate having first and second principal surfaces opposite each other; and a collector layer, a base layer, and an emitter layer stacked in this order on the first principal surface side of the semiconductor substrate. The collector layer includes a first semiconductor layer with metal particles dispersed therein, the metal particles each formed by a plurality of metal atoms bonded with each other.Type: GrantFiled: November 22, 2017Date of Patent: July 16, 2019Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Shigeru Yoshida, Masahiro Shibata
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Publication number: 20190172933Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.Type: ApplicationFiled: November 30, 2018Publication date: June 6, 2019Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Shigeki KOYA, Masao KONDO, Takayuki TSUTSUI
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Publication number: 20190109066Abstract: A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.Type: ApplicationFiled: October 5, 2018Publication date: April 11, 2019Applicant: Murata Manufacturing Co., Ltd.Inventors: Masao KONDO, Masahiro SHIBATA
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Publication number: 20190088768Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.Type: ApplicationFiled: September 7, 2018Publication date: March 21, 2019Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Shigeki KOYA, Masao KONDO, Takayuki TSUTSUI
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Patent number: 10212364Abstract: The zoom control apparatus configured to control an angle of view. The apparatus includes a motion acquirer configured to acquire a motion amount of an image capturing optical system, a calculator configured to calculate a displacement amount of a main object image in a captured image by using the motion amount of the image capturing optical system, a determiner configured to determine whether or not the displacement amount of the main object image is larger than a first threshold, and a controller configured to perform, when the displacement amount of the main object image is larger than the first threshold, control for making the angle of view wider than that for when the displacement amount of the main object image is smaller than the first threshold.Type: GrantFiled: December 13, 2016Date of Patent: February 19, 2019Assignee: Canon Kabushiki KaishaInventors: Masahiro Shibata, Tomohiro Sugaya
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Patent number: 10174453Abstract: A composition improves mechanical strength (e.g., impact resistance and flexural strength), and achieves improved mass productivity by reducing a situation in which a strand fuzzes during extrusion. The composition includes a conjugated diene-based polymer (A), fibers (B), and a thermoplastic resin (C), the composition including the conjugated diene-based polymer (A) in a ratio of 0.05 to 30 parts by mass based on 100 parts by mass of the thermoplastic resin (C), and including the fibers (B) in a ratio of 3 to 150 parts by mass based on 100 parts by mass of the thermoplastic resin (C), wherein the conjugated diene-based polymer (A) includes at least one functional group selected from the group consisting of an alkoxysilyl group and an amino group.Type: GrantFiled: July 3, 2015Date of Patent: January 8, 2019Assignee: JSR CORPORATIONInventors: Shuugo Maeda, Akihiko Morikawa, Kentarou Kanae, Teruo Aoyama, Jirou Ueda, Masahiro Shibata, Akihiko Ookubo
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Publication number: 20190006306Abstract: A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface.Type: ApplicationFiled: June 12, 2018Publication date: January 3, 2019Applicant: Murata Manufacturing Co., Ltd.Inventors: Masahiro SHIBATA, Daisuke TOKUDA, Atsushi KUROKAWA, Hiroaki TOKUYA, Yasunari UMEMOTO
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Publication number: 20180372970Abstract: An optical connecting device includes: a holder having a first end, a second end, and a through hole extending in a direction of a first axis from one of the first end and the second end to the other; multiple optical fibers held by the holder; a guide member extending in the through hole; and a resin body separating a side face of the guide member from an inner face of the through hole.Type: ApplicationFiled: June 25, 2018Publication date: December 27, 2018Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Mitsuharu Hirano, Akira Furuya, Koichi Koyama, Masahiro Shibata
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Patent number: 10163829Abstract: A compound semiconductor substrate has a first main surface parallel to a first direction and a second direction perpendicular to the first direction, a second main surface located on a side opposite to the first main surface, and a recess. The recess has an opening, a bottom surface facing the opening, and a plurality of side surfaces located between the opening and the bottom surface. The side surfaces include at least one first side surface forming an angle of about ? degrees with the bottom surface in the recess and at least one second side surface forming an angle of about ? degrees with the bottom surface in the recess. The total length of edge lines between the first main surface and the at least one first side surface is larger than that of edge lines between the first main surface and the at least one second side surface.Type: GrantFiled: December 6, 2017Date of Patent: December 25, 2018Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata
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Publication number: 20180309417Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.Type: ApplicationFiled: April 5, 2018Publication date: October 25, 2018Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Kenichi NAGURA