Patents by Inventor Masahiro Shioda
Masahiro Shioda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8977120Abstract: In an apparatus for accommodating and multiplexing asynchronous client signals in which an idle signal is defined, the transmission side transmits client signals after synchronizing the client signals by inserting or removing, with reference to a specific client signal, an idle signal to/from the same type of another client signal, and in the receiving side, a PLL part is shared by recovering a clock from a client signal and distributing the clock for another client signal.Type: GrantFiled: March 11, 2011Date of Patent: March 10, 2015Assignees: Nippon Telegraph and Telephone Corporation, Fujitsu LimitedInventors: Takuya Ohara, Takashi Ono, Shigeki Aisawa, Masahito Tomizawa, Hiroyuki Honma, Satoru Saitoh, Masahiro Shioda
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Patent number: 8965197Abstract: A node device in an optical transport ring network including plural node devices connected in a ring form using plural optical transmission paths so that optical transport frames of a working line and a protection line are transmitted using the plural optical transmission paths, includes a control information transmitter, when a failure occurs in the optical transmission paths, transmitting the optical transport frame to an opposing node device as a transmission destination node in the optical transmission paths, the optical transport frame including switching control information; and a switcher receiving the optical transport frame including switching control information, the optical transport frame being transmitted to the node device as the transmission destination node, forming a loop back to fold a transmission path between the plural optical transmission paths, and switching the optical transmission path from the work line to the protection line.Type: GrantFiled: June 25, 2012Date of Patent: February 24, 2015Assignee: Fujitsu LimitedInventors: Katsuhiro Shirai, Koji Takeguchi, Takashi Honda, Masahiro Shioda
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Patent number: 8824507Abstract: A transmitting apparatus includes a frame dividing circuit that maps frame data of each of a plurality of frames whose period is different from each other into one or a plurality of internal frames having a fixed frame period and a fixed transmission rate, based on a predetermined internal clock; a cross-connect circuit that cross-connects the frame data of each in a time division multiplexing system based on the internal clock in units of the internal frames; and a frame combining circuit that demaps, into any of the plurality of frames, or multiplexes, data of one or a plurality of internal frames cross-connected by the cross-connect circuit.Type: GrantFiled: May 3, 2012Date of Patent: September 2, 2014Assignee: Fujitsu LimitedInventors: Hiroyuki Honma, Masahiro Shioda, Toru Katagiri
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Patent number: 8705974Abstract: An optical transmission system transmits an optical signal of multi-level modulation. In a transmitter module, a data string in a specified frame is rearranged into a plurality of logical lanes. A lane ID, which specifies in what logical lane out of the plurality of logical lanes a start of the data string is arranged, is assigned to a non-scrambled area in an overhead portion of the frame. The lane ID corresponding to one of the plurality of logical lanes is different from the lane IDs corresponding to the other remaining logical lanes. The optical signal is generated using the data string rearranged into the plurality of logical lanes. In a receiver, the lane ID is detected according to a majority method. The inversion of bits and the swapping of lanes are detected using the lane ID and compensated.Type: GrantFiled: March 5, 2012Date of Patent: April 22, 2014Assignee: Fujitsu LimitedInventors: Yohei Koganei, Masahiro Shioda, Osamu Takeuchi, Hayato Furukawa, Yasuhiko Aoki
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Patent number: 8687655Abstract: A signal demultiplexer includes a conversion unit that converts a format of a high speed signal transfer frame output from a terminating unit into a format of a converted frame; a parallelization unit that parallelizes the converted frame and outputs a predetermined number of data columns; and a separating unit that separates plural low speed signal transfer frames from the predetermined number of the data columns. The conversion unit converts the format of the high speed signal transfer frame into the format of the converted frame by delaying a signal storing area using first and second overhead areas, to include an “i” th tributary slot among the predetermined number of the tributary slots assigned to the signal storing area into an arbitrary “i” th data column among the predetermined number of the data columns, and to align front positions of the predetermined number of the data columns.Type: GrantFiled: February 21, 2012Date of Patent: April 1, 2014Assignee: Fujitsu LimitedInventors: Toru Katagiri, Masahiro Shioda
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Patent number: 8675684Abstract: A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.Type: GrantFiled: March 8, 2010Date of Patent: March 18, 2014Assignee: Fujitsu LimitedInventors: Toru Katagiri, Masahiro Shioda
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Patent number: 8478137Abstract: An optical receiver includes: a waveform distortion compensator to perform an operation on digital signal representing an optical signal generated by an A/D converter to compensate for waveform distortion of the optical signal; a phase detector to generate phase information representing sampling phase of the A/D converter; a phase adjuster to generate digital signal representing an optical signal in which the sampling phase of the A/D converter is adjusted from an output signal of the waveform distortion compensator using the phase information; a demodulator to generate a demodulated signal from the output signal of the phase adjuster; a phase controller to control the sampling phase of the A/D converter; a peak detector to detect a peak value of the phase information while the sampling phase of the A/D converter is controlled by the phase controller; and a compensation controller to control the waveform distortion compensator using the peak value.Type: GrantFiled: January 31, 2011Date of Patent: July 2, 2013Assignee: Fujitsu LimitedInventors: Kosuke Komaki, Masahiro Shioda, Katsumi Fukumitsu, Osamu Takeuchi
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Publication number: 20130058643Abstract: A data amount derivation apparatus includes: a first calculator configured to derive, for one series of parallelized mapping signals, amount of data in each frame period for a frame into which the parallelized mapping signals are mapped; and a second calculator configured to sum up amounts of data in N frame periods, where N is an integer, and to derive the resulting summation value as the amount of data to be mapped into the frame, each of the amounts of data in each of the frame periods being derived by the first calculator.Type: ApplicationFiled: October 31, 2012Publication date: March 7, 2013Applicant: FUJITSU LIMITEDInventors: Hiroyuki HONMA, Toru Katagiri, Hiromichi Makishima, Masahiro Shioda, Hiroyuki Kitajima, Ichiro Yokokura
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Publication number: 20130004168Abstract: In an apparatus for accommodating and multiplexing asynchronous client signals in which an idle signal is defined, the transmission side transmits client signals after synchronizing the client signals by inserting or removing, with reference to a specific client signal, an idle signal to/from the same type of another client signal, and in the receiving side, a PLL part is shared by recovering a clock from a client signal and distributing the clock for another client signal.Type: ApplicationFiled: March 11, 2011Publication date: January 3, 2013Applicants: FUJITSU LIMITED, NIPPON TELEGRAPH AND TELEPHONE CORPORATIONInventors: Takuya Ohara, Takashi Ono, Shigeki Aisawa, Masahito Tomizawa, Hiroyuki Honma, Satoru Saitoh, Masahiro Shioda
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Patent number: 8331793Abstract: An optical transmission apparatus including a transmitting OTL processor to rearrange a data string stored in a frame into a plurality of logical lanes, and set a lane ID used to identify in which logical lane a beginning of the data string is arranged among the plurality of logical lanes in a non-scramble area in an overhead of the frame, and a receiving OTL processor to respectively identify the lane IDs included in the data string in the respective physical lanes rearranged, determine a generation state of a bit inversion and a lane replacement for each physical lane, compensate the bit inversion and the lane replacement so that the data string in the respective physical lanes becomes same state as the data string in the respective logical lanes, based on the identified result, and rearrange the compensated data string in the respective logical lanes so as to regenerate the frame.Type: GrantFiled: June 11, 2010Date of Patent: December 11, 2012Assignee: Fujitsu LimitedInventors: Osamu Takeuchi, Masahiro Shioda, Yasuhiko Aoki, Hisao Nakashima
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Publication number: 20120281985Abstract: A transmitting apparatus includes a frame dividing circuit that maps frame data of each of a plurality of frames whose period is different from each other into one or a plurality of internal frames having a fixed frame period and a fixed transmission rate, based on a predetermined internal clock; a cross-connect circuit that cross-connects the frame data of each in a time division multiplexing system based on the internal clock in units of the internal frames; and a frame combining circuit that demaps, into any of the plurality of frames, or multiplexes, data of one or a plurality of internal frames cross-connected by the cross-connect circuit.Type: ApplicationFiled: May 3, 2012Publication date: November 8, 2012Applicant: FUJITSU LIMITEDInventors: Hiroyuki HONMA, Masahiro Shioda, Toru Katagiri
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Publication number: 20120263452Abstract: A node device in an optical transport ring network including plural node devices connected in a ring form using plural optical transmission paths so that optical transport frames of a working line and a protection line are transmitted using the plural optical transmission paths, includes a control information transmitter, when a failure occurs in the optical transmission paths, transmitting the optical transport frame to an opposing node device as a transmission destination node in the optical transmission paths, the optical transport frame including switching control information; and a switcher receiving the optical transport frame including switching control information, the optical transport frame being transmitted to the node device as the transmission destination node, forming a loop back to fold a transmission path between the plural optical transmission paths, and switching the optical transmission path from the work line to the protection line.Type: ApplicationFiled: June 25, 2012Publication date: October 18, 2012Applicant: FUJITSU LIMITEDInventors: Katsuhiro SHIRAI, Koji TAKEGUCHI, Takashi HONDA, Masahiro SHIODA
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Publication number: 20120230350Abstract: A signal demultiplexer includes a conversion unit that converts a format of a high speed signal transfer frame output from a terminating unit into a format of a converted frame; a parallelization unit that parallelizes the converted frame and outputs a predetermined number of data columns; and a separating unit that separates plural low speed signal transfer frames from the predetermined number of the data columns. The conversion unit converts the format of the high speed signal transfer frame into the format of the converted frame by delaying a signal storing area using first and second overhead areas, to include an “i” th tributary slot among the predetermined number of the tributary slots assigned to the signal storing area into an arbitrary “i” th data column among the predetermined number of the data columns, and to align front positions of the predetermined number of the data columns.Type: ApplicationFiled: February 21, 2012Publication date: September 13, 2012Applicant: FUJITSU LIMITEDInventors: Toru KATAGIRI, Masahiro Shioda
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Publication number: 20120219282Abstract: An optical transmission system transmits an optical signal of multi-level modulation. In a transmitter module, a data string in a specified frame is rearranged into a plurality of logical lanes. A lane ID, which specifies in what logical lane out of the plurality of logical lanes a start of the data string is arranged, is assigned to a non-scrambled area in an overhead portion of the frame. The lane ID corresponding to one of the plurality of logical lanes is different from the lane IDs corresponding to the other remaining logical lanes. The optical signal is generated using the data string rearranged into the plurality of logical lanes. In a receiver, the lane ID is detected according to a majority method. The inversion of bits and the swapping of lanes are detected using the lane ID and compensated.Type: ApplicationFiled: March 5, 2012Publication date: August 30, 2012Applicant: FUJITSU LIMITEDInventors: Yohei KOGANEI, Masahiro Shioda, Osamu Takeuchi, Hayato Furukawa, Yasuhiko Aoki
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Publication number: 20110200339Abstract: An optical receiver includes: a waveform distortion compensator to perform an operation on digital signal representing an optical signal generated by an A/D converter to compensate for waveform distortion of the optical signal; a phase detector to generate phase information representing sampling phase of the A/D converter; a phase adjuster to generate digital signal representing an optical signal in which the sampling phase of the A/D converter is adjusted from an output signal of the waveform distortion compensator using the phase information; a demodulator to generate a demodulated signal from the output signal of the phase adjuster; a phase controller to control the sampling phase of the A/D converter; a peak detector to detect a peak value of the phase information while the sampling phase of the A/D converter is controlled by the phase controller; and a compensation controller to control the waveform distortion compensator using the peak value.Type: ApplicationFiled: January 31, 2011Publication date: August 18, 2011Applicant: FUJITSU LIMITEDInventors: Kosuke KOMAKI, Masahiro Shioda, Katsumi Fukumitsu, Osamu Takeuchi
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Patent number: 7940651Abstract: A read address from a memory and a write address to the memory are transmitted from a VT pointer circuit on an active side to a VT pointer circuit on a standby side in order to eliminate a difference between pointer values of the VT pointer circuits on the active and the standby sides, which is caused by a difference between the phases of the read address from the memory and the write address to the memory of the VT pointer circuits on the active and the standby sides, and the read and the write addresses on the standby side are overwritten with the transmitted address values. As a result, the address values can be made to match both on the active and the standby sides, and also the pointer values can be made to match.Type: GrantFiled: May 31, 2006Date of Patent: May 10, 2011Assignee: Fujitsu LimitedInventors: Masahiro Shioda, Mitsuhiro Kawaguchi, Hideki Matsui, Mitsumasa Matsuike
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Publication number: 20100322630Abstract: An optical transmission apparatus including a transmitting OTL processor to rearrange a data string stored in a frame into a plurality of logical lanes, and set a lane ID used to identify in which logical lane a beginning of the data string is arranged among the plurality of logical lanes in a non-scramble area in an overhead of the frame, and a receiving OTL processor to respectively identify the lane IDs included in the data string in the respective physical lanes rearranged, determine a generation state of a bit inversion and a lane replacement for each physical lane, compensate the bit inversion and the lane replacement so that the data string in the respective physical lanes becomes same state as the data string in the respective logical lanes, based on the identified result, and rearrange the compensated data string in the respective logical lanes so as to regenerate the frame.Type: ApplicationFiled: June 11, 2010Publication date: December 23, 2010Applicant: FUJITSU LIMITEDInventors: Osamu TAKEUCHI, Masahiro Shioda, Yasuhiko Aoki, Hisao Nakashima
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Publication number: 20100226648Abstract: A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.Type: ApplicationFiled: March 8, 2010Publication date: September 9, 2010Applicant: FUJITSU LIMITEDInventors: Toru Katagiri, Masahiro Shioda
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Patent number: RE47127Abstract: A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.Type: GrantFiled: March 17, 2016Date of Patent: November 13, 2018Assignee: FUJITSU LIMITEDInventors: Toru Katagiri, Masahiro Shioda
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Patent number: RE48932Abstract: A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.Type: GrantFiled: January 17, 2018Date of Patent: February 15, 2022Assignee: FUJITSU LIMITEDInventors: Toru Katagiri, Masahiro Shioda