Patents by Inventor Masahiro Shioda

Masahiro Shioda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100226648
    Abstract: A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.
    Type: Application
    Filed: March 8, 2010
    Publication date: September 9, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Toru Katagiri, Masahiro Shioda
  • Patent number: 7778160
    Abstract: A transmission device in which a bus of a central processing unit is used to synchronize timing signals between units, thereby restraining enlargement in scale of wiring. A reference signal generator generates a reference signal. A reference signal receiver is mounted on a unit set as an active or standby unit and receives the reference signal. A timing signal generator divides the frequency of the received reference signal by means of a frequency divider/counter to generate a timing signal. A count holder holds the count value of the frequency divider/counter. The bus connects the units and the central processing unit. A count receiver receives, via the bus, the count value from the count holder of the active unit. A count updater updates the count value of the frequency divider/counter to the count value received by the count receiver.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: August 17, 2010
    Assignee: Fujitsu Limited
    Inventors: Takashi Kaiga, Koichi Sugama, Tsutomu Chikazawa, Yukio Katayanagi, Kenichi Yajima, Hideo Abe, Ryuji Kayama, Masahiro Shioda
  • Patent number: 7639702
    Abstract: A plug-in card for an optical transmission apparatus includes a J1generating unit. The J1 generating unit sends information on on-use side J1 data to a plug-in card at a spare side in a redundant structure when the plug-in card operates as an on-use side plug-in card. The J1 generating unit receives information on on-use side J1 data from a plug-in card at the on-use side when the plug-in card operates as a spare side plug-in card. Based on the information, the J1 generating unit matches spare side J1 data to the on-use side J1 data. The plug-in card also includes a B3 byte calculating unit that operates in a similar way as the J1 generating unit does in processing B3 byte data.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: December 29, 2009
    Assignee: Fujitsu Limited
    Inventors: Hideki Matsui, Mitsuhiro Kawaguchi, Masahiro Shioda, Ryuji Kayama, Takashi Kaiga
  • Patent number: 7418203
    Abstract: An object of the invention is to provide a diagnosis method for standby systems in an optical ring network having a redundant configuration, which can confirm normal states of standby systems in all optical transmission apparatuses on the network, even during operations of active systems. To this end, in the present diagnosis method for standby systems, when a diagnosis start command is given to an arbitrary optical transmission apparatus on the network, the optical transmission apparatus provides a false signal to a standby system unit to diagnoses an operation state thereof, and transmits the result to the optical transmission apparatus on the downstream side by utilizing overhead information in the active system optical channel.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 26, 2008
    Assignee: Fujitsu Limited
    Inventors: Masahiro Shioda, Junji Yamamoto
  • Publication number: 20080037592
    Abstract: A transmission device in which a bus of a central processing unit is used to synchronize timing signals between units, thereby restraining enlargement in scale of wiring. A reference signal generator generates a reference signal. A reference signal receiver is mounted on a unit set as an active or standby unit and receives the reference signal. A timing signal generator divides the frequency of the received reference signal by means of a frequency divider/counter to generate a timing signal. A count holder holds the count value of the frequency divider/counter. The bus connects the units and the central processing unit. A count receiver receives, via the bus, the count value from the count holder of the active unit. A count updater updates the count value of the frequency divider/counter to the count value received by the count receiver.
    Type: Application
    Filed: July 19, 2007
    Publication date: February 14, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Kaiga, Koichi Sugama, Tsutomu Chikazawa, Yukio Katayanagi, Kenichi Yajima, Hideo Abe, Ryuji Kayama, Masahiro Shioda
  • Publication number: 20070263646
    Abstract: A plug-in card for an optical transmission apparatus includes a J1 byte generating unit. The J1 byte generating unit sends information on on-use side J1 byte data to a plug-in card at a spare side in a redundant structure when the plug-in card operates as an on-use side plug-in card. The J1 byte generating unit receives information on on-use side J1 byte data from a plug-in card at the on-use side when the plug-in card operates as a spare side plug-in card. Based on the information, the J1 byte generating unit matches spare side J1 byte data to the on-use side J1 byte data. The plug-in card also includes a B3 byte calculating unit that operates in a similar way as the J1 byte generating unit does in processing B3 byte data.
    Type: Application
    Filed: September 28, 2006
    Publication date: November 15, 2007
    Inventors: Hideki Matsui, Mitsuhiro Kawaguchi, Masahiro Shioda, Ryuji Kayama, Takashi Kaiga
  • Publication number: 20070189155
    Abstract: A read address from a memory and a write address to the memory are transmitted from a VT pointer circuit on an active side to a VT pointer circuit on a standby side in order to eliminate a difference between pointer values of the VT pointer circuits on the active and the standby sides, which is caused by a difference between the phases of the read address from the memory and the write address to the memory of the VT pointer circuits on the active and the standby sides, and the read and the write addresses on the standby side are overwritten with the transmitted address values. As a result, the address values can be made to match both on the active and the standby sides, and also the pointer values can be made to match.
    Type: Application
    Filed: May 31, 2006
    Publication date: August 16, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Masahiro SHIODA, Mitsuhiro Kawaguchi, Hideki Matsui, Mitsumasa Matsuike
  • Patent number: 7225366
    Abstract: A transport systems is equipped with a burst error detecting unit that monitors a predetermined byte, which is specified in advance in a frame to be monitored, in a transmission signal having header information and data information multiplexed into the frame in bytes. The burst error detecting unit detects a burst error based on a change in a state of occurrence of a bit error in the predetermined byte in a predetermined time window.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: May 29, 2007
    Assignee: Fujitsu Limited
    Inventors: Hideaki Arao, Masahiro Shioda
  • Publication number: 20050180318
    Abstract: The invention relates to a subordinate apparatus and a superordinate apparatus. The object thereof is to surely detecting an erroneous connection in a wiring between these apparatus and identifying an erroneously connected cable. A subordinate apparatus has an identifier acquiring section acquiring an identifier that is granted by a superordinate apparatus via a communication link that is formed via a first cable. When granted a new identifier via the communication link, the identifier acquiring section makes a first judgment as to whether there is an identifier granted prior to the new identifier. The identifier acquiring section nullifies the new identifier if there is an identifier granted prior to the new identifier.
    Type: Application
    Filed: June 18, 2004
    Publication date: August 18, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki Yamamoto, Masahiro Shioda
  • Publication number: 20050169629
    Abstract: An object of the invention is to provide a diagnosis method for standby systems in an optical ring network having a redundant configuration, which can confirm normal states of standby systems in all optical transmission apparatuses on the network, even during operations of active systems. To this end, in the present diagnosis method for standby systems, when a diagnosis start command is given to an arbitrary optical transmission apparatus on the network, the optical transmission apparatus provides a false signal to a standby system unit to diagnoses an operation state thereof, and transmits the result to the optical transmission apparatus on the downstream side by utilizing overhead information in the active system optical channel.
    Type: Application
    Filed: June 30, 2004
    Publication date: August 4, 2005
    Applicant: Fujitsu Limited
    Inventors: Masahiro Shioda, Junji Yamamoto
  • Patent number: 6895182
    Abstract: An optical transmission technique for a ring transmission system that can transmit time-division-multiplexed optical signals in dual directions. An optical transmitting apparatus comprises a data link reading section, a topology creating section, a data link writing section, a squelch table creating section, a squelch table, an RIP table creating section, an RIP table, a node recognizing section, an east-side receiving unit, an east-side transmitting unit, a west-side transmitting unit, and a west-side receiving unit. When a transmission route is switched at plural positions, the squelch table and the RIP table are automatically created as soon as a crossconnect is set. With minimum setting, the ring transmission system can be normally operated without increasing the number of setting items, the squelch table can be created at a high speed using existing hardware, and an alarm can be automatically transmitted from a secondary node until each table is created.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: May 17, 2005
    Assignee: Fujitsu Limited
    Inventors: Junichi Moriyama, Tsutomu Chikazawa, Yoshihisa Ikeda, Takanori Yasui, Atsuki Taniguchi, Masahiro Shioda
  • Publication number: 20040205444
    Abstract: A transport systems is equipped with a burst error detecting unit that monitors a predetermined byte, which is specified in advance in a frame to be monitored, in a transmission signal having header information and data information multiplexed into the frame in bytes. The burst error detecting unit detects a burst error based on a change in a state of occurrence of a bit error in the predetermined byte in a predetermined time window.
    Type: Application
    Filed: January 30, 2004
    Publication date: October 14, 2004
    Inventors: Hideaki Arao, Masahiro Shioda
  • Patent number: 6763038
    Abstract: In a light transmission equipment which can generate a desired concatenation signal from a maximum concatenation signal standardized in a synchronous transmission mode, a master and a slave circuit for clock change are provided respectively inputting at least two data at a maximum transmission rate based on a concatenation standard of a synchronous transmission mode obtained by dividing a desired transmission rate not prescribed in the concatenation standard to perform a concatenation control to the slave circuit by control information from the master circuit side.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: July 13, 2004
    Assignee: Fujitsu Limited
    Inventors: Nobuhiko Usui, Koji Matsunaga, Masayuki Maehira, Tatsuya Toyozumi, Yumiko Ogata, Masahiro Shioda, Atsuki Taniguchi
  • Patent number: 6728925
    Abstract: In an error correcting method and an apparatus therefor using Hamming codes, a frame regulated by a synchronous network is divided into L blocks in the direction of row. Preferably, information bits and check bits are allocated to a payload portion and non-defined bits of an LOH portion, respectively. More preferably, the information bits and the check bits are divided into M sub blocks to form a Hamming code block. In addition, a code error correcting means rearrange each Hamming code block per bit and further preferable, a syndrome register with a plurality of banks operates an error syndrome of the Hamming code block, and based on the operation result, the code error correction of the Hamming code block is performed by a bank switchover.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: April 27, 2004
    Assignee: Fujitsu Limited
    Inventors: Junichi Ishiwatari, Atsuki Taniguchi, Masahiro Shioda, Takashi Kuwabara, Yukio Yamazaki
  • Patent number: 6587459
    Abstract: A TSA circuit which receives as input upper side incoming transmission data from a super high speed ring network and lower side incoming transmission data from a high speed ring network and outputs upper side outgoing transmission data to the super high speed ring network and lower side outgoing transmission data to the high speed ring network, provided with a time slot assignment function block which has a time switch and a space switch and produces outgoing transmission data obtained by switching channels for the incoming transmission data in units of bits, whereby high speed and large volume incoming transmission data can be processed for time slot assignment (TSA), interchanged in channels, and sent out as outgoing transmission data by a relatively small sized circuit configuration.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: July 1, 2003
    Assignee: Fujitsu Limited
    Inventors: Yukio Suda, Satoshi Nemoto, Masahiro Shioda, Takashi Kuwabara
  • Publication number: 20030061562
    Abstract: In an error correcting method and an apparatus therefor using Hamming codes, a frame regulated by a synchronous network is divided into L blocks in the direction of row. Preferably, information bits and check bits are allotted to a payload portion and an LOH portion of non-defined bits. More preferably, the information bits and the check bits are divided into M subblocks to form a Hamming code block. In addition, a code error correcting means rearrange each Hamming code block per bit and further preferably, a syndrome register with a plurality of banks operates an error syndrome of the Hamming code block, and based on the operation result, the code error correction of the Hamming code block is performed by a bank switchover.
    Type: Application
    Filed: May 25, 1999
    Publication date: March 27, 2003
    Inventors: JUNICHI ISHIWATARI, ATSUKI TANIGUCHI, MASAHIRO SHIODA, TAKASHI KUWABARA, YUKIO YAMAZAKI
  • Patent number: 6343068
    Abstract: The present invention relates to a guard apparatus for avoiding the malfunction of a communication apparatus due to an error in the received data in the specific location of a frame on the receiving side of an optical communication system using a SONET/SDH network. If a B2 error, a frame pattern error or an out-of-frame is detected for a received frame, this guard apparatus stops the operation for tri-stage protection for the data of the K1 and K2 bytes, and outputs data outputted for a received frame received one frame before the above-mentioned received frame. If these errors are not detected, the guard apparatus selects and outputs the non-protected data of the K1 and K2 bytes in the above-mentioned received frame. Thus, the extraction of data with an error due to an optical degradation can be avoided and thereby the malfunction of a communication apparatus in an optical communication system can be avoided.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: January 29, 2002
    Assignee: Fujitsu Limited
    Inventors: Chiyoko Yamamoto, Masahiro Shioda
  • Patent number: 6330237
    Abstract: A time slot assignment circuit capable of performing channel setting with a high efficiency and with a high degree of freedom of channel setting with respect to a large volume of transmission data and in addition having a small circuit scale and low power consumption, provided a time switch provided with a transmission data memory into which transmission data is sequentially written and performing switching in a time domain with respect to the transmission data, a space switch for performing switching in a space domain with respect to an output thereof, an address control memory which outputs a channel setting address for controlling the two switches, and a channel setting information converting unit for converting a channel setting information from the outside to a channel setting address and an accessing address for the memory.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: December 11, 2001
    Assignee: Fujitsu Limited
    Inventors: Yukio Suda, Satoshi Nemoto, Yasuhiro Murakami, Masahiro Shioda
  • Patent number: 5909298
    Abstract: An optical telecommunication unit includes a shielded case having a size adapted for mounting upon a standard open-rack frame, wherein the shielded case includes a rear panel carrying an interconnection pattern, a plurality of plug-in connectors provided on the rear panel at an inner side thereof in electrical connection with the interconnection pattern for holding plug-in units forming an optical telecommunication apparatus inside the optical telecommunication unit, wherein the optical telecommunication unit carries a plurality of interface connectors on the rear panel in electrical connection with the interconnection pattern for accepting external interconnection cables, and a rear cover is provided on the shielded case so as to cover the rear panel.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: June 1, 1999
    Assignee: Fujitsu Limited
    Inventors: Shozo Shimada, Kiyonori Kusuda, Hirofumi Imabayashi, Katsuya Fujii, Tetsuya Takahashi, Masahiro Shioda
  • Patent number: 5546403
    Abstract: A bidirectional line switch ring network wherein, when a fault occurs in the ring transmission line, a loopback is formed at the node adjoining the fault so as to loop back the line between a first optical fiber and a second optical fiber and therefore protect the line. The time slot numbers of the working line time slots and the time slot numbers of the line protection time slots allotted in the first optical fiber and the time slot numbers of the working line time slots and the time slot numbers of the line protection time slots allotted in the second optical fiber are set to be respectively the same. By this, the configuration and control of the hardware handling the loopback switching are simplified.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: August 13, 1996
    Assignee: Fujitsu Limited
    Inventors: Chiyoko Yamamoto, Daisuke Maruhashi, Masahiro Shioda