Abstract: A method for manufacturing a fluorescent lamp that can achieve stable luminous characteristics and discharge characteristics and also does not suffer from cracks in the interconnected portion of the glass tubes while handling or lighting the fluorescent lamp is provided. Interconnecting portions located in the vicinity of open end portions of glass tubes that are positioned adjacent to each other are heated respectively from inside to form a welding portion, and then, the glass tubes are thrust against each other and thinned by conducting a preliminary tapping of the welding portion from inside using hammers. Next, the welding portion is opened by conducting a main tapping to form an interconnected portion, and end portions in the vicinity of the interconnected portion are closed by heating and melting, and then the end portions are molded.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain—drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. The drain-gate connection layer has an extension section extending in a direction toward the drain-gate connection layer. The drain-gate connection layer 41b has an extension section extending in a direction toward the drain-gate connection layer.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain—drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. Driver transistors of one memory cell do not commonly share the n+ type source region with driver transistors of another memory cell.

Abstract: A semiconductor device includes an SRAM section and a logic circuit section formed on a single semiconductor substrate. First and second gate electrode layers located in a first conductive layer, first and second drain-drain contact layers located in a second conductive layer, first and second drain-gate contact layers located in a third conductive layer become conductive layers for forming a flip-flop of the SRAM section. The logic circuit section has no wiring layer at the same level as the first and second drain-drain contact layers.

Abstract: An intravascular obstruction removing wire includes an elongate wire body, at least two non-branched wire portions having distal ends and proximal ends which are connected to a distal end of the wire main body, and a plurality of filament portions extending across the wire portions. The non-branched wire portions and the filament portions form a trapping portion. The trapping portion is deformable from a large-diameter state in which the non-branched portions branch to the distal end of the wire body forward in different directions and the filament portions are separated from each other, so that a space surrounded by the non-branched wire portions and the filament portions is formed to trap therein an obstruction in a blood vessel, to a small-diameter state in which the non-branched wire portions are positioned so that a distance between the wire portions is smaller than that of the wire portions in the large-diameter state.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define connection wirings of a flip-flop. A p+ type well contact region is provided for every two of the memory cells arranged in the Y-axis direction.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. A source contact layer of load transistors are located adjacent end sections of the gate electrode layers, and both of the end sections bend outwardly to avoid contact with the source contact layer.

Abstract: First and second gate electrode layers located in a first conductive layer, first and second drain-drain connecting layers located in a second conductive layer, and first and second drain-gate connecting layers located in a third conductive layer become conductive layers for forming a flip-flop. First and second contact-conductive sections are formed in a region from an interlayer dielectric between the first and second conductive layers to an interlayer dielectric between the second and third conductive layers. The first drain-gate connecting layer is connected to the second gate electrode layer with the first contact-conductive section interposed. The second drain-gate connecting layer is connected to the first gate electrode layer with the second contact-conductive section interposed.

Abstract: First and second gate electrode layers that are positioned in a first conductive layer, first and second drain-drain contact layers that are positioned in a second conductive layer, and first and second drain-gate contact layers that are positioned in a third conductive layer together form conductive layers for a flip-flop. A sub word line extends in the X-axis direction in the first conductive layer. A VDD wire is disposed extending in the X-axis direction in the second conductive layer. A main word line is disposed extending in the X-axis direction in the third conductive layer. A bit line, a bit line/, a VSS wire, and a VDD wire are disposed extending in the Y-axis direction in the fourth conductive layer.

Abstract: The drain of a drive transistor Q3 and the drain of a load transistor Q5 are connected by a first drain—drain contact layer. The drain of a drive transistor Q4 and the drain of a load transistor Q6 are connected by a second drain—drain contact layer. The gate electrodes of the drive transistor Q3 and the load transistor Q5 (a first gate electrode layer) are connected to the second drain—drain contact layer by a first drain-gate contact layer. The gate electrodes of the drive transistor Q4 and the load transistor Q6 (a second gate electrode layer) are connected to the first drain—drain contact layer by a second drain-gate contact layer.

Abstract: A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transistors are formed in the first n-well. The second n-well is located under the p-well and the first n-well and also is connected to the first n-well. The potential of the first n-well is supplied from the second n-well. According to the present invention, the SRAM section can be reduced in size.

Abstract: A semiconductor device having trench isolation regions in which leaks are suppressed may be formed using the following steps. (a) Forming a trench 32 in a semiconductor layer 12; (b) forming a dielectric layer 40 that fills the trench 32; and (c) conducting a thermal treatment of the dielectric layer 40, wherein the thermal treatment is conducted at temperatures of 1050° C. or higher.

Abstract: A method for manufacturing a fluorescent lamp that can achieve stable luminous characteristics and discharge characteristics and also does not suffer from cracks in the interconnected portion of the glass tubes while handling or lighting the fluorescent lamp is provided. Interconnecting portions located in the vicinity of open end portions of glass tubes that are positioned adjacent to each other are heated respectively from inside to form a welding portion, and then, the glass tubes are thrust against each other and thinned by conducting a preliminary tapping of the welding portion from inside using hammers. Next, the welding portion is opened by conducting a main tapping to form an interconnected portion, and end portions in the vicinity of the interconnected portion are closed by heating and melting, and then the end portions are molded.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. A source contact layer of load transistors are located adjacent end sections of the gate electrode layers, and both of the end sections bend outwardly to avoid contact with the source contact layer.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define connection wirings of a flip-flop. A p+ type well contact region is provided for every two of the memory cells arranged in the Y-axis direction.

Abstract: A semiconductor memory device comprising first and second gate electrode layers in a first conductive layer, first and second drain-drain connecting layers in a second conductive layer, and first and second drain-gate connecting layers in a third conductive layer. The first and second drain-gate connecting layers are located higher than the first and second gate electrode layers. Therefore, a source contact layer can be located in the region between gate electrode layers while preventing a contact with the second drain-gate connecting layer.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. The drain-gate connection layer has an extension section extending in a direction toward the drain-gate connection layer. The drain-gate connection layer 41b has an extension section extending in a direction toward the drain-gate connection layer.

Abstract: The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. Driver transistors of one memory cell do not commonly share the n+ type source region with driver transistors of another memory cell.

Abstract: The drain of a drive transistor Q3 and the drain of a load transistor Q5 are connected by a first drain-drain contact layer. The drain of a drive transistor Q4 and the drain of a load transistor Q6 are connected by a second drain-drain contact layer. The gate electrodes of the drive transistor Q3 and the load transistor Q5 (a first gate electrode layer) are connected to the second drain-drain contact layer by a first drain-gate contact layer. The gate electrodes of the drive transistor Q4 and the load transistor Q6 (a second gate electrode layer) are connected to the first drain-drain contact layer by the second drain-gate contact layer.

Abstract: A semiconductor memory device comprising first and second gate electrode layers in a first conductive layer, first and second drain-drain connecting layers in a second conductive layer, and first and second drain-gate connecting layers in a third conductive layer. The first and second drain-gate connecting layers are located higher than the first and second gate electrode layers. Therefore, a source contact layer can be located in the region between gate electrode layers while preventing a contact with the second drain-gate connecting layer.