Abstract: This invention provides a method for forming a catalyst layer for carbon nanostructure growth, which can eliminate the influence of water in a liquid for catalyst layer formation, can grow homogeneous and highly oriented carbon nanostructures over the whole area of a substrate and can realize mass production of the carbon nanostructures, and a liquid for catalyst layer formation for use in the method, and a process for producing carbon nanostructures using the catalyst layer formed by the method. The catalyst layer for use in the production of CNTs is formed by preparing a catalyst metal salt solution of a catalyst metal-containing metal compound (a catalyst metal salt) dispersed or dissolved in a solvent having an ample wettability towards the substrate and coating the catalyst metal salt solution onto the substrate to a form a thin film. The thin film is then heat treated to form a catalyst layer.

Abstract: This invention provides a method for forming a catalyst layer for carbon nanostructure growth, which can eliminate the influence of water in a liquid for catalyst layer formation, can grow homogeneous and highly oriented carbon nanostructures over the whole area of a substrate and can realize mass production of the carbon nanostructures, and a liquid for catalyst layer formation for use in the method, and a process for producing carbon nanostructures using the catalyst layer formed by the method. The catalyst layer for use in the production of CNTs is formed by preparing a catalyst metal salt solution of a catalyst metal-containing metal compound (a catalyst metal salt) dispersed or dissolved in a solvent having an ample wettability towards the substrate and coating the catalyst metal salt solution onto the substrate to a form a thin film. The thin film is then heat treated to form a catalyst layer.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: This is a cathode ray tube having a panel provided with a colored layer on an outer surface of a face portion, wherein an emission luminance ratio is 75% or higher in a lowest part relative to a highest part, and a diffuse reflectance ratio is 90% or higher in a lowest part relative to a highest part in an image display area of the face portion. Due to this configuration, a cathode ray tube with a natural appearance can be obtained in which a luminance difference or a contrast difference is not perceived in the entire area of the face portion.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: In a method of treating a surface of a face panel for an image display including forming a film on the surface using coating materials, the film is formed of at least two layers including a first layer formed by a spray coating method and a second layer formed by a spin coating method to be superposed on the first layer. Thus, a face plate having antireflection/antistatic effects and providing high-resolution images can be obtained with high efficiency.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: A face panel used for an image display device is provided efficiently at a low cost, and the face panel has functions such as antireflection and it provides images with excellent resolution and contrast. The face panel is surface-treated by forming at least one coating film by spraying on the panel a coating material including microparticles. The coating material contains a solvent of ethylene glycol, propylene glycol ether, water and an alcohol having 1-3 carbon atoms.

Abstract: This is a cathode ray tube having a panel provided with a colored layer on an outer surface of a face portion, wherein an emission luminance ratio is 75% or higher in a lowest part relative to a highest part, and a diffuse reflectance ratio is 90% or higher in a lowest part relative to a highest part in an image display area of the face portion. Due to this configuration, a cathode ray tube with a natural appearance can be obtained in which a luminance difference or a contrast difference is not perceived in the entire area of the face portion.

Abstract: In a method of treating a surface of a face panel for an image display including forming a film on the surface using coating materials, the film is formed of at least two layers including a first layer formed by a spray coating method and a second layer formed by a spin coating method to be superposed on the first layer. Thus, a face plate having antireflection/antistatic effects and providing high-resolution images can be obtained with high efficiency.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.

Abstract: A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitu

Abstract: A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; a

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: An output from an OCL type power output circuit is applied to a loudspeaker load through a switching means such as a relay. A first detector circuit and a second detector circuit detect a first operating status (e.g., output d.c. level) and a second operating status (e.g., output current level of an output transistor) of the OCL type power output circuit, respectively. The detection output signals of the first detector circuit and the second detector circuit are respectively applied to a first detecting transistor and a second detecting transistor. In the normal operation status of the OCL type power output circuit, the first detecting transistor and the second detecting transistor are respectively biased into "on" states by the first detector circuit and the second detector circuit so as to permit predetermined currents to flow. When the first and second detecting transistors are in their "on" states they control a driving transistor into an "on" state.