Abstract: The present invention provides a secure buffer for use in data storage and encryption processing. Blocks or packets of data are passed to a secure buffer within a processor. The processor may be one of many coprocessors, and the secure buffer may be inaccessible to some or all of the coprocessors. Data may be partially or fully encrypted and stored within the secure buffer. Encryption may occur before or after storage in the buffer, or it may take place within the buffer itself. Optionally, the encrypted data may be sent to and retrieved from a shared memory that is accessible by other coprocessors.

Abstract: A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.

Abstract: A parallelization permission and prohibition management unit of a processor manages the permission or prohibition of the parallelization for each combination of partial spaces in cooperation with another parallelization permission and prohibition management unit of a different processor. Specifically, when any given object is present across the boundary between a first partial space and a second partial space, the parallelization is prohibited between the collision process to be performed by any given processor on the virtual objects in the first partial space and the collision process to be performed by another processor on the virtual object in the second partial space.

Abstract: Methods and apparatus for migrating and distributing processor tasks on a plurality of multi-processing systems distributed over a network. The multi-processing system includes at least one broadband entity, each broadband entity including a plurality of processing units and synergistic processing units, as well as a shared memory. Tasks from one broadband entity are bundled, migrated and processed remotely on other broadband entities to efficiently use processing resources, and then returned to the migrating broadband entity for completion or continued processing.

Abstract: Methods and apparatus provide for associating memory allocation table (MAT) entries with nodes in a binary tree such that the nodes and the entries are grouped into hierarchical levels, each entry including status information; associating the nodes and the entries with segments of a shared memory of a multi-processor system such that higher level nodes and entries are associated with larger numbers of segments of the shared memory and lower level nodes and entries are associated with smaller numbers of segments of the shared memory; initializing the MAT such that the status information of at least a plurality of entries indicates that the associated segment or segments of the shared memory are available for reservation; and selecting one entry in a group of entries in the MAT at a level corresponding to a desired size of the shared memory to be reserved.

Abstract: A system and method is provided for improved interrupt handling via a micro interrupt handler. Upon an interrupt signal being sent to a processor running a task, a first part of the running task is stored to system memory via direct memory access. A micro interrupt handler is read from the system memory to begin handling the interrupt signal. A second part of the running task is stored to system memory via direct memory access. The micro interrupt handler is executed and read and the previous running task is read from direct memory access and restored. Long lag times for interrupt processing and inefficiencies in processor queues are avoided.

Abstract: A method of and apparatus for compressing a stream of data, such as video data, is disclosed. First, data in the video stream are classified in accordance with their values. Data with values equal to zero are classified in a first class. Data with values less than a predetermined positive number but greater than a predetermined negative number, and not equal to zero, are classified in a second class. All other data are classified in a third class. Data in the first class is compressed using a run length encoding technique. Data in the second class is compressed by reducing the size of the data value and by adding a constant. Data in the third class is not compressed, but is modified by adding a constant. The data can be decompressed by determining the class of the compressed value and reversing the compression process. The compression method disclosed is easy to implement and results in a significant reduction in the amount of data that needs to be transmitted.

Abstract: A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.

Abstract: A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.

Abstract: Methods and apparatus are provided for managing processor tasks in a multi-processor computing system. The system is operable to store the processor tasks in a shared memory that may be accessed by a plurality of sub-processing units of the multi-processor computing system; and permit the sub-processing units to determine which of the processor tasks should be copied from the shared memory and executed based on priorities of the processor tasks.

Abstract: Methods and apparatus provide a processor for operative connection to a main memory for storing data, the processor being operable to request at least some of the data for use; and a local memory in operative connection with the processor such that the data may be stored therein for use by the processor, the local memory not being a hardware cache memory, wherein the processor is operable to execute application program interface code that configures the local memory to include at least one software invoked cache memory area therein.

Abstract: The present multi-processor system performs information processing suitably. The system can receive, reproduce and record a variety of image contents. By comprising a powerful CPU in the multi-processors, a plurality of pieces of large image data, such as high definition image data or the like, can be processed simultaneously in parallel, which was difficult conventionally. Since task processing, such as demodulation processing or the like, is assigned respectively in view of the remaining processing capacity of each of the plurality of processors, the system can reproduce contents efficiently. By sharing roles, a plurality of different contents, such as an image, a voice, or the like can be processed simultaneously and can be displayed or reproduced at a desired timing.

Abstract: A synchronization scheme is provided for a multiprocessor system. In particular, a processor includes a buffer sync controller. The buffer sync controller is operative to allow or deny access by a subprocessor to shared data in a shared memory, such that a processor seeking to write data into or read data from the shared memory must ascertain certain shared parameter data processed by the buffer sync controller.

Abstract: Methods and apparatus provide for associating memory allocation table (MAT) entries with nodes in a binary tree such that the nodes and the entries are grouped into hierarchical levels, each entry including status information; associating the nodes and the entries with segments of a shared memory of a multi-processor system such that higher level nodes and entries are associated with larger numbers of segments of the shared memory and lower level nodes and entries are associated with smaller numbers of segments of the shared memory; initializing the MAT such that the status information of at least a plurality of entries indicates that the associated segment or segments of the shared memory are available for reservation; and selecting one entry in a group of entries in the MAT at a level corresponding to a desired size of the shared memory to be reserved.

Abstract: A parallelization permission and prohibition management unit of a processor manages the permission or prohibition of the parallelization for each combination of partial spaces in cooperation with another parallelization permission and prohibition management unit of a different processor. Specifically, when any given object is present across the boundary between a first partial space and a second partial space, the parallelization is prohibited between the collision process to be performed by any given processor on the virtual objects in the first partial space and the collision process to be performed by another processor on the virtual object in the second partial space.

Abstract: Methods and apparatus provide for associating memory allocation table (MAT) entries with nodes in a binary tree such that the nodes and the entries are grouped into hierarchical levels, each entry including status information; associating the nodes and the entries with segments of a shared memory of a multi-processor system such that higher level nodes and entries are associated with larger numbers of segments of the shared memory and lower level nodes and entries are associated with smaller numbers of segments of the shared memory; initializing the MAT such that the status information of at least a plurality of entries indicates that the associated segment or segments of the shared memory are available for reservation; and selecting one entry in a group of entries in the MAT at a level corresponding to a desired size of the shared memory to be reserved.

Abstract: A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least important processor as far as task priority is concerned, it will then select and transfer its interrupt-related responsibilities (i.e., handling the interrupt and determining the next interrupt-handing processor) to the processor which is executing the least important task. The selected processor will then be designated for handling interrupts unless and until it undergoes a task switch and selects a different processor.

Abstract: The present invention provides a secure buffer for use in data storage and encryption processing. Blocks or packets of data are passed to a secure buffer within a processor. The processor may be one of many coprocessors, and the secure buffer may be inaccessible to some or all of the coprocessors. Data may be partially or fully encrypted and stored within the secure buffer. Encryption may occur before or after storage in the buffer, or it may take place within the buffer itself. Optionally, the encrypted data may be sent to and retrieved from a shared memory that is accessible by other coprocessors.

Abstract: Methods and apparatus enable the execution of processing sequences including the computation of a register index that is loaded into one of a plurality of registers, utilizing that index to identify another of the plurality of registers, and accessing data from or copying data to the indexed register to or from yet another register or a memory location.

Abstract: A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address in a second portion of the instruction, evaluating the value to determine whether a condition is met, and pre-fetching one or more instructions starting at the target instruction address into an instruction buffer of the processor when the condition is met, is provided.