Abstract: A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least important processor as far as task priority is concerned, it will then select and transfer its interrupt-related responsibilities (i.e., handling the interrupt and determining the next interrupt-handing processor) to the processor which is executing the least important task. The selected processor will then be designated for handling interrupts unless and until it undergoes a task switch and selects a different processor.

Abstract: Methods and apparatus for migrating and distributing processor tasks on a plurality of multi-processing systems distributed over a network. The multi-processing system includes at least one broadband entity, each broadband entity including a plurality of processing units and synergistic processing units, as well as a shared memory. Tasks from one broadband entity are bundled, migrated and processed remotely on other broadband entities to efficiently use processing resources, and then returned to the migrating broadband entity for completion or continued processing.

Abstract: Methods and apparatus are provided for: grouping objects within a three dimensional (3D) graphics space into a plurality of object sets, each object set being located in a respective sub-space within the 3D space; computing final graphics data for each object of the object sets based on initial graphics data for each of the objects, where the respective computations for each of the object sets are performed using a respective one of a plurality of processors of a multi-processor system; and repeating the above steps for each of a plurality of image frames using the final graphics data from a previous image frame as the initial graphics data for a current image frame.

Abstract: Methods and apparatus provide for executing one or more software programs within a plurality of processors of a multi-processing system in accordance with a data parallel processing model, the software programs being comprised of a number of processing tasks, each task executing instructions on one or more input data units to produce an output data unit, and each data unit containing one or more data objects; responding to one or more application programming interface codes to change from a current processing task to a subsequent processing task within a given one or more of the processors; and using the output data unit produced by the current processor task as an input data unit by the subsequent processing task to produce a further output data unit within the same processor.

Abstract: A system and method is provided for improved interrupt handling via a micro interrupt handler. Upon an interrupt signal being sent to a processor running a task, a first part of the running task is stored to system memory via direct memory access. A micro interrupt handler is read from the system memory to begin handling the interrupt signal. A second part of the running task is stored to system memory via direct memory access. The micro interrupt handler is executed and read and the previous running task is read from direct memory access and restored. Long lag times for interrupt processing and inefficiencies in processor queues are avoided.

Abstract: A method of and apparatus for compressing a stream of data, such as video data, is disclosed. First, data in the video stream are classified in accordance with their values. Data with values equal to zero are classified in a first class. Data with values less than a predetermined positive number but greater than a predetermined negative number, and not equal to zero, are classified in a second class. All other data are classified in a third class. Data in the first class is compressed using a run length encoding technique. Data in the second class is compressed by reducing the size of the data value and by adding a constant. Data in the third class is not compressed, but is modified by adding a constant. The data can be decompressed by determining the class of the compressed value and reversing the compression process. The compression method disclosed is easy to implement and results in a significant reduction in the amount of data that needs to be transmitted.

Abstract: A synchronization scheme is provided for a multiprocessor system. In particular, a processor includes a buffer sync controller. The buffer sync controller is operative to allow or deny access by a subprocessor to shared data in a shared memory, such that a processor seeking to write data into or read data from the shared memory must ascertain certain shared parameter data processed by the buffer sync controller.

Abstract: Methods and apparatus provide for associating memory allocation table (MAT) entries with nodes in a binary tree such that the nodes and the entries are grouped into hierarchical levels, each entry including status information; associating the nodes and the entries with segments of a shared memory of a multi-processor system such that higher level nodes and entries are associated with larger numbers of segments of the shared memory and lower level nodes and entries are associated with smaller numbers of segments of the shared memory; initializing the MAT such that the status information of at least a plurality of entries indicates that the associated segment or segments of the shared memory are available for reservation; and selecting one entry in a group of entries in the MAT at a level corresponding to a desired size of the shared memory to be reserved.

Abstract: The present invention provides for rendering photorealistic 3D viewing angles. Lighting values are approximated across selected viewing angles. In fixed lighting situations, approximating across viewing angles allows rendering of a high order lighting detail with complex surfaces. A polynomial equation representing the surfaces will be solved for the coefficients to be used in the formula of the fixed viewing angle. If the number of light sources is too high only specular and diffusion surfaces can be efficiently calculated in the polynomial equation.

Abstract: Methods and apparatus provide a processor for operative connection to a main memory for storing data, the processor being operable to request at least some of the data for use; and a local memory in operative connection with the processor such that the data may be stored therein for use by the processor, the local memory not being a hardware cache memory, wherein the processor is operable to execute application program interface code that configures the local memory to include at least one software invoked cache memory area therein.

Abstract: Methods and apparatus enable the execution of processing sequences including the computation of a register index that is loaded into one of a plurality of registers, utilizing that index to identify another of the plurality of registers, and accessing data from or copying data to the indexed register to or from yet another register or a memory location.

Abstract: Methods and apparatus are provided for managing processor tasks in a multi-processor computing system. The system is operable to store the processor tasks in a shared memory that may be accessed by a plurality of sub-processing units of the multi-processor computing system; and permit the sub-processing units to determine which of the processor tasks should be copied from the shared memory and executed based on priorities of the processor tasks.

Abstract: An arbitrator provided to a processor element requests the utilization of a bus sends a bus request signal and a bus request value according to a priority level of the processor element to the bus, determines the priority of utilizing the bus in accordance with utilizing situation of the bus and the priority level of the processor element. Since a common bus arbitrating circuit connected to the bus watches the bus and determines a processor element to utilize the bus according to the utilizing situation of the bus and the priority level of the processor elements requesting the utilization of the bus, the bus arbitration can be performed with high speed, and an increase of communication speed between the processor elements through a single bus can be realized.

Abstract: A system wherein raw material excavated from a plurality of pit faces on a mine are conveyed to and collected at a specific collecting location at the foot of a mountain by a plurality of vehicles and the degree of quality of collected raw material is then properly controlled at the specific collecting location is generally called a mining site control process. To practically execute such a mining control process, the degree of quality of conveyed raw material previously analyzed per each pit face and a quantity of conveyance thereof are confirmed at every time when the raw material is conveyed to the collecting location.

Abstract: A bearingless hub structure for rotary-wing aircrafts comprising a hub body ecured to a rotor shaft, a plurality of radially extending flexbeams integrally formed with the hub body, and pitch housings enclosing each of the flexbeams in spaced relationship, the pitch housing having a radially outer end portion rigidly secured to an inboard end of a rotor blade and a radially inner end portion supported by a spherical bearing in the vicinity of a root end of said flexbeam.The flexbeam consists of a flexible element of low lead-lag stiffness and a torsion element of low torsional stiffness located radially outside the flexible element. The flexible element consists of two beam-like members having radially inner ends spaced in the lead-lag direction and extending radially outward with narrowing the distance between them, the beam-like member having radially outer end connected to a radially inner end of the torsion element.