Abstract: On a front surface of an n+-type SiC substrate becoming a drain region, an n?-type drift layer, a p-type base layer, and an n+-type source layer are sequentially formed by epitaxial growth. In the n+-type source layer, the p+-type contact region is selectively provided. A trench is provided penetrating the n+-type source layer and the p-type base layer in the depth direction and reaching the n?-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 ?m or less. A depth of the trench is, for example, 1 ?m or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.

Abstract: In a semiconductor device, an IGBT and an SJMOSFET connected in parallel have respective gate terminals controlled independently of each other. When a high voltage occurs and a high current flows caused by short-circuit in an external circuit under a condition of ON state of the IGBT and SJMOSFET, an operational amplifier in the control IC detects the overcurrent through the IGBT and controls the gate signal to restrict the current through the IGBT. After that, the operational amplifier throttles the current through the IGBT according to a reference voltage of a capacitor decreasing by the discharge through a constant current source, thus conducting soft-OFF operation of the IGBT.

Abstract: An SJ-MOSFET and IGBT are provided in a single semiconductor chip. Furthermore, a balance is made between a carrier amount of n-type columns and a carrier amount of p-type columns, to encourage formation of a depletion layer in when a reverse voltage is applied in the SJ-MOSFET section. Provided is a includes a semiconductor substrate, a super junction structure formed on a front surface side of the semiconductor substrate, and a field stop layer formed at a position overlapping with the super junction structure on a back surface side of the semiconductor substrate, in a manner to not contact an end of the super junction structure on the back surface side.

Abstract: To improve a tradeoff between ON voltage and ON/OFF loss while maintaining short-circuit tolerance, provided is a semiconductor device including an IGBT element; a super junction transistor element connected in parallel with the IGBT element; and a limiting section that limits a voltage applied to a gate terminal of the IGBT element more than a voltage applied to a gate terminal of the super junction transistor element.

Abstract: On a front surface of an n+-type SiC substrate becoming a drain region, an n?-type drift layer, a p-type base layer, and an n+-type source layer are sequentially formed by epitaxial growth. In the n+-type source layer, the p+-type contact region is selectively provided. A trench is provided penetrating the n+-type source layer and the p-type base layer in the depth direction and reaching the n?-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 ?m or less. A depth of the trench is, for example, 1 ?m or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.

Abstract: A MOS gate structure is provided on a p-type base layer side of a silicon carbide semiconductor base formed by sequentially forming on a front surface of an n+-type silicon carbide substrate, an n-type drift layer and a p-type base layer by epitaxial growth. On the base front surface, in an edge termination structure region, a step portion occurring between the p-type base layer and the n-type drift layer, and a flat portion farther outward than the step portion are provided. In a surface layer of the n-type drift layer, a p+-type base region constituting the MOS gate structure is provided so as to contact the p-type base layer. The outermost p+-type base region extends from an active region into the flat portion and the entire lower side of this portion is covered by an innermost p?-type region constituting an edge termination structure provided in the flat portion.

Abstract: A MOS gate structure is provided on a p-type base layer side of a silicon carbide semiconductor base formed by sequentially forming on a front surface of an n+-type silicon carbide substrate, an n-type drift layer and a p-type base layer by epitaxial growth. On the base front surface, in an edge termination structure region, a step portion occurring between the p-type base layer and the n-type drift layer, and a flat portion farther outward than the step portion are provided. In a surface layer of the n-type drift layer, a p+-type base region constituting the MOS gate structure is provided so as to contact the p-type base layer. The outermost p+-type base region extends from an active region into the flat portion and the entire lower side of this portion is covered by an innermost p?-type region constituting an edge termination structure provided in the flat portion.

Abstract: To improve a tradeoff between ON voltage and ON/OFF loss while maintaining short-circuit tolerance, provided is a semiconductor device including an IGBT element; a super junction transistor element connected in parallel with the IGBT element; and a limiting section that limits a voltage applied to a gate terminal of the IGBT element more than a voltage applied to a gate terminal of the super junction transistor element.

Abstract: An SJ-MOSFET and IGBT are provided in a single semiconductor chip. Furthermore, a balance is made between a carrier amount of n-type columns and a carrier amount of p-type columns, to encourage formation of a depletion layer in when a reverse voltage is applied in the SJ-MOSFET section. Provided is a includes a semiconductor substrate, a super junction structure formed on a front surface side of the semiconductor substrate, and a field stop layer formed at a position overlapping with the super junction structure on a back surface side of the semiconductor substrate, in a manner to not contact an end of the super junction structure on the back surface side.

Abstract: In order to realize an SJ-MOSFET and an IGBT on a single chip and realize a new arrangement configuration for an SJ-MOSFET section and an IGBT section in a single semiconductor chip, provided is a semiconductor device including a semiconductor substrate; two or more super-junction transistor regions provided on the semiconductor substrate; and one or more IGBT regions that are provided in regions sandwiched by the two or more super-junction transistor regions, in a cross section obtained by cleaving along a pane perpendicular to the semiconductor substrate.

Abstract: In a semiconductor device, an IGBT and an SJMOSFET connected in parallel have respective gate terminals controlled independently of each other. When a high voltage occurs and a high current flows caused by short-circuit in an external circuit under a condition of ON state of the IGBT and SJMOSFET, an operational amplifier in the control IC detects the overcurrent through the IGBT and controls the gate signal to restrict the current through the IGBT. After that, the operational amplifier throttles the current through the IGBT according to a reference voltage of a capacitor decreasing by the discharge through a constant current source, thus conducting soft-OFF operation of the IGBT.

Abstract: In order to realize an SJ-MOSFET and an IGBT on a single chip and realize a new arrangement configuration for an SJ-MOSFET section and an IGBT section in a single semiconductor chip, provided is a semiconductor device including a semiconductor substrate; two or more super-junction transistor regions provided on the semiconductor substrate; and one or more IGBT regions that are provided in regions sandwiched by the two or more super-junction transistor regions, in a cross section obtained by cleaving along a pane perpendicular to the semiconductor substrate.

Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Abstract: A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior long-term forward blocking voltage capability reliability, and which allows minimal forward blocking voltage capability variation. The edge termination structure has multiple ring-like p-type guard rings, a first insulating film covering the guard rings, and ring-like field plates, provided via the first insulating film atop the guard rings. The field plates have a polysilicon film and a thicker metal film. The polysilicon film is provided on a first guard ring via first insulating film, and a dual field plate made of the polysilicon film and metal film is provided on a second guard ring. The dual field plate is stacked via a second insulating film. The first and second guard rings alternate.

Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Abstract: A trench MOSFET includes mesa regions between the trenches. The mesa regions are connected to an emitter electrode to fix the mesa region potential so that the mesa regions do not form a floating structure. P-type base regions are distributed in the mesa regions, and the distributed p-type base regions (e.g., the limited regions in the mesa regions) are provided with an emitter structure. The trench MOSFET can lower the switching losses, reducing the total losses while suppressing the ON-state voltage drop of the trench IGBT as low as the ON-state voltage drop of the IEGT, and improving the turn-on characteristics thereof. The trench MOSFET also can reduce the capacitance between the gates and the emitter thereof, since the regions where the gate electrode faces the emitter structure are reduced. The trench MOSFET can have trench gate structures set at a narrow interval to relax the electric field localization to the bottom portions of the trenches and obtain a high breakdown voltage.

Abstract: A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25?{N1/(N1+N2)}×100?75.

Abstract: A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior long-term forward blocking voltage capability reliability, and which allows minimal forward blocking voltage capability variation. The edge termination structure has multiple ring-like p-type guard rings, a first insulating film covering the guard rings, and ring-like field plates, provided via the first insulating film atop the guard rings. The field plates have a polysilicon film and a thicker metal film. The polysilicon film is provided on a first guard ring via first insulating film, and a dual field plate made of the polysilicon film and metal film is provided on a second guard ring. The dual field plate is stacked via a second insulating film. The first and second guard rings alternate.

Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.