Patents by Inventor Masahito Otsuki

Masahito Otsuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5559355
    Abstract: Mutual interference is reduced between a main cell portion and a sensing cell portion for detecting the current flowing through the main cell portion of a vertical MOS semiconductor device, and accuracy and reliability of overcurrent detection are improved. In the device, well regions of (p) type are formed between the main and sensing cell portions for capturing the minority carriers. Breakdown of the gate oxide film caused by an open emitter electrode of the sensing cell portion is prevented by forming the (p) type well regions with ring shapes, by spacing the (p) type well regions by 5 to 20 .mu.m, and by adjusting the isolation withstand voltage between the main and sensing cell portions below the withstand voltage of the gate oxide film. A voltage spike is minimized by narrowing the overlap of the detecting and gate electrodes for reduced capacitance between these electrodes.
    Type: Grant
    Filed: June 20, 1995
    Date of Patent: September 24, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tomoyuki Yamazaki, Shigeyuki Obinata, Masahito Otsuki, Seiji Momota, Tatsuhiko Fujihira
  • Patent number: 5559347
    Abstract: An insulated gate-type bipolar transistor with an overcurrent limiting function that is capable of keeping the ratio of a main current to a detection current constant even under different operating conditions, and capable of suppressing the voltage dependence of the limited-current value to perform stable overcurrent protection. P-wells are formed so that they are incorporated between main cell IGBTs as sensing cells for current detection on part of the semiconductor substrate on which a large number of main cells are formed integratedly, and current-detecting emitter electrodes connected to the P-wells are connected to an overcurrent-protection circuit and separated from the main emitter electrodes connected to the main IGBT cells.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: September 24, 1996
    Assignee: Fuji Electronic Co., Ltd.
    Inventors: Tomoyuki Yamazaki, Masahito Otsuki
  • Patent number: 5530277
    Abstract: An insulated-gate bipolar transistor is formed of a number of cells integrally formed on a semiconductor substrate. The cells includes main cells with emitter electrodes, and current detection sensing cells situated adjacent to the main cells. Emitter electrodes are formed in an area of the sensing cells to be separated from the emitter electrodes of the main cells, and an overcurrent protection circuit is connected to the emitter electrodes of the sensing cells. When shorting accident occurs, an overcurrent protecting operation is performed such that an overcurrent is accurately detected through the sensing cells and a main current flowing through the main cells is made smaller than a short-circuit withstanding capacity of the IGBT by gate control of the protection circuit.
    Type: Grant
    Filed: October 12, 1994
    Date of Patent: June 25, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masahito Otsuki, Shigeyuki Obinata, Yukio Yano
  • Patent number: 5459339
    Abstract: A semiconductor device thyristor structure includes a first conductive type collector region, second conductive type and first conductive type base regions, and a second conductive type emitter region. First conductive type regions and second conductive type regions have respective first and second type majority carriers. A first MOSFET injects the second type majority carriers into the second conductive type base region. A second MOSFET is opened and closed independent of the first MOSFET and extracts the first type majority carriers from the first conductive type base region. A third MOSFET has a first gate electrode which is also a gate electrode of the first MOSFET, for extracting the first type majority carriers from the first conductive type base region. First conductive type and second conductive type emitter regions are formed within the first conductive type base region and an emitter voltage can be simultaneously applied to these emitter regions.
    Type: Grant
    Filed: April 29, 1993
    Date of Patent: October 17, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Ken'ya Sakurai, Masahito Otsuki, Noriho Terasawa, Tadashi Miyasaka, Akira Nishiura, Masaharu Nishiura
  • Patent number: 5397905
    Abstract: In a semiconductor device having insulated gate field effect transistors and bipolar transistors, a buried layer of a first conductivity type having an impurity concentration higher than that of a second layer of the first conductivity type is disposed in at least a lower region between a second layer of a second conductivity type and a third layer of the second conductivity type and in the vicinity of a boundary between the second layer of the first conductivity type, which serves as back gates of the field effect transistors and base layers of the bipolar transistors, and the first layer of the second conductivity type.
    Type: Grant
    Filed: February 15, 1994
    Date of Patent: March 14, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masahito Otsuki, Katsunori Ueno
  • Patent number: 5378903
    Abstract: The semiconductor device is formed of an EST part and an IGBT part, wherein the EST part has a first MOSFET and a second MOSFET synchronously switching, and the IGBT part has a third MOSFET controllable independently from them. At a turn-off of the semiconductor device, when turning off the first and second MOSFETs while keeping the third MOSFET at an on-state, IGBT operation remains. Thus, the current path which tends to flow to an emitter region changes toward an emitter electrode side even if the recovery of the potential barrier is late due to the junction in the emitter region, and the charge accumulation to the emitter region is restrained. After the potential barrier is recovered, the third MOSFET is turned off. Controllable turn-off current can be enlarged and turn-off time can be shortened.
    Type: Grant
    Filed: March 22, 1994
    Date of Patent: January 3, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masahito Otsuki, Katsunori Ueno