Patents by Inventor Masahito Takahashi

Masahito Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nonvolatile semiconductor memory with selectively driven word lines
    Patent number: 5455789
    Abstract: Two paths for receiving the outputs of a logic select circuit LOGS are individually equipped in a symmetric manner with output MOSFETs Q52 and Q53, feedback MOSFETs Q54 and Q55 and isolating MOSFETs Q56 and Q57, the paired of which have conduction types different from each other. Negative erasing Vee voltage and programming Vpp voltage to be fed to the paths through the feedback MOSFETs are prevented without fail from being transmitted to a logic select circuit by the paired isolating MOSFETs of the different conduction types. As the elements for selecting the positive or negative logic output of the logic select circuit, CMOS transfer gates TG1 and TG2 can be adopted to maximize the amplitude of the output logic signal of the logic select circuit with respect to an operating power.
    Type: Grant
    Filed: May 10, 1994
    Date of Patent: October 3, 1995
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takeshi Nakamura, Masashi Wada, Masahito Takahashi, Hiroshi Sato, Takeshi Furuno