Abstract: A first reception processing unit performs a process of receiving a first signal transmitted on a first transmission line, a second reception processing unit performs a process of receiving a second signal transmitted on a second transmission line, and an output speed control unit controls output speeds of the first signal and the second signal subjected to the reception process. A system switching unit selects and outputs the first signal or the second signal subjected to a reception process, and an output processing unit performs a process for output to another apparatus on the output from the system switching unit. A reception side clock output unit outputs a clock signal giving a processing timing of each process, and a clock frequency control unit adjusts a frequency of the clock signal giving the processing timing to the output processing unit.

Abstract: A transmission apparatus includes redundant first communication devices configured to communicate with a communication apparatus provided in a first network, and redundant second communication devices configured to communicate with a communication apparatus provided in a second network. The second communication devices include respective first ends that are ends of redundant communication paths of the first communication devices, and the first communication devices include respective second ends that are ends of redundant communication paths of the second communication devices.

Abstract: An electric digital received signal obtained from a received optical signal is segmented into blocks of a certain length with an overlap of a length determined in advance with an adjacent block. Fourier transformation is performed for each of the blocks. The blocks subjected to the Fourier transformation are stored consecutively in time series, a coefficient determined based on a wavelength dispersion compensation amount according to one of frequency positions and a delay amount according to one of the frequency positions and one of time positions is applied to each of frequency component values included in a plurality of the stored blocks, and the blocks to which the coefficient has been applied and which are obtained by adding up the frequency component values to which the coefficient has been applied for each of the frequency positions are generated. Inverse Fourier transformation is performed on the generated blocks to which the coefficient has been applied.

Abstract: A signal processing device includes a distributing unit and a plurality of correcting units with different processing performance, the distributing unit distributes a bit sequence having a first number of bits to the first correcting unit, and a bit sequence having a second number of bits less than the first number of bits to the second correcting unit having lower processing performance than the first correcting unit, the first correcting unit applies error correction processing to the bit sequence having the first number of bits distributed to the first correcting unit, and the second correcting unit applies error correction processing to the bit sequence having the second number of bits distributed to the second correcting unit.

Abstract: A transmission apparatus includes a control unit for carrying out processing to secure a resource for a standby system path in response to detection of a sign of failure in an active system path.

Abstract: An electric digital received signal obtained from a received optical signal is segmented into blocks of a certain length with an overlap of a length determined in advance with an adjacent block. Fourier transformation is performed for each of the blocks. The blocks subjected to the Fourier transformation are stored consecutively in time series, a coefficient determined based on a wavelength dispersion compensation amount according to one of frequency positions and a delay amount according to one of the frequency positions and one of time positions is applied to each of frequency component values included in a plurality of the stored blocks, and the blocks to which the coefficient has been applied and which are obtained by adding up the frequency component values to which the coefficient has been applied for each of the frequency positions are generated. Inverse Fourier transformation is performed on the generated blocks to which the coefficient has been applied.

Abstract: An error correction device includes a first correction unit which performs error correction decoding of data by a repetitive operation, having a full operation state in which the error correction decoding is repeated until convergence is obtained and a save operation state in which the number of times of the repetitive operation is restricted to a predetermined number. An error information estimation unit estimates an input error rate or an output error rate of the first correction unit using a decoding result of the first correction unit, and a control unit which controls transition between the full operation state and the save operation state based on at least one piece of information of the input error rate, the output error rate, and an operation time of the first correction unit. It is thus possible to provide an error correction device that can improve a transmission characteristic while suppressing power consumption.

Abstract: A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination.

Abstract: A first reception processing unit performs a process of receiving a first signal transmitted on a first transmission line, a second reception processing unit performs a process of receiving a second signal transmitted on a second transmission line, and an output speed control unit controls output speeds of the first signal and the second signal subjected to the reception process. A system switching unit selects and outputs the first signal or the second signal subjected to a reception process, and an output processing unit performs a process for output to another apparatus on the output from the system switching unit. A reception side clock output unit outputs a clock signal giving a processing timing of each process, and a clock frequency control unit adjusts a frequency of the clock signal giving the processing timing to the output processing unit.

Abstract: A transmission apparatus performs communication with a transmission side transmission apparatus via a transmission path of an active system and a transmission path of a standby system. The transmission apparatus includes: a memory configured to have a capacity that is as large as delay caused due to a maximum path difference between the transmission path of the active system and the transmission path of the standby system is allowable; and a memory connection control unit configured to switch connection of the memory and cause a signal of the transmission path of the active system or the transmission path of the standby system to be accumulated in the memory.

Abstract: A transmission apparatus includes redundant first communication devices configured to communicate with a communication apparatus provided in a first network, and redundant second communication devices configured to communicate with a communication apparatus provided in a second network. The second communication devices include respective first ends that are ends of redundant communication paths of the first communication devices, and the first communication devices include respective second ends that are ends of redundant communication paths of the second communication devices.

Abstract: A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination.

Abstract: A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination.

Abstract: A signal processing device includes a distributing unit and a plurality of correcting units with different processing performance, the distributing unit distributes a bit sequence having a first number of bits to the first correcting unit, and a bit sequence having a second number of bits less than the first number of bits to the second correcting unit having lower processing performance than the first correcting unit, the first correcting unit applies error correction processing to the bit sequence having the first number of bits distributed to the first correcting unit, and the second correcting unit applies error correction processing to the bit sequence having the second number of bits distributed to the second correcting unit.

Abstract: A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination.

Abstract: An error correction device according to this invention includes a first correction unit configured to perform error correction decoding of data by a repetitive operation, and having a full operation state in which the repetitive operation of the error correction decoding is repeated until convergence is obtained and a save operation state in which the number of times of the repetitive operation of the error correction decoding is restricted to a predetermined number of times, an error information estimation unit configured to estimate an input error rate or an output error rate of the first correction unit using a decoding result of the first correction unit, and a control unit configured to control transition between the full operation state and the save operation state of the first correction unit based on at least one piece of information of the input error rate, the output error rate, and an operation time of the first correction unit.

Abstract: A plurality of error correction circuits corrects errors of the data transmitted through the plurality of transmission lines. A combining portion combines the plurality of transmission lines to the plurality of error correction circuits. The plurality of transmission lines includes a first transmission line, and a second transmission line having a lower transmission characteristic than the first transmission line. The plurality of error correction circuits includes a first and a second error correction circuit having lower error correction capability and power consumption than the first error correction circuit. The combining portion uses a function to combine a plurality of error correction circuits with one transmission path, combines the first transmission line with the second error correction circuit at a higher rate than the first error correction circuit, and combines the second transmission line with the first error correction circuit at a higher rate than the second error correction circuit.

Abstract: A band division timing adjustment unit aligns timings of a plurality of signals, which are generated by dividing a received signal according to a plurality of frequency bands, in a time domain and combines the plurality of signals for which the timings have been aligned. A chromatic dispersion compensation unit compensates chromatic dispersion of an output signal of the band division timing adjustment unit for each of the plurality of frequency bands.

Abstract: A reception circuit includes a first adaptive compensator compensating distortion of a received signal. An adaptive compensation coefficient calculator includes a known-signal detector detecting first and second known-signals from the received signal, a second adaptive compensator compensating distortion of the received signal, a tap coefficient initial value calculator calculating an initial value of a tap coefficient of the second adaptive compensator by comparing the first known-signal with its true value, a first phase shift compensator compensating phase shift of an output of the second adaptive compensator using the second known-signal, and a tap coefficient calculator calculating tap coefficients of the first and second adaptive compensators by comparing at least one of the first and second known-signals compensated by the second adaptive compensator and the first phase shift compensator with its true value.

Abstract: A band division timing adjustment unit (10) aligns timings of a plurality of signals, which are generated by dividing a received signal according to a plurality of frequency bands, in a time domain and combines the plurality of signals for which the timings have been aligned. A chromatic dispersion compensation unit (17) compensates chromatic dispersion of an output signal of the band division timing adjustment unit (10) for each of the plurality of frequency bands.