Abstract: According to an embodiment, the threshold value generation unit generates a setting voltage and converts the setting voltage to a first current. One end of the first resistor is connected to a detection terminal. When a voltage applied to the detection terminal is greater than or equal to a predetermined factor times the voltage of the higher voltage source, the detection unit causes a constant detection terminal input current to flow from the detection terminal to the first resistor. When the voltage at the detection terminal is less than the predetermined factor times the voltage of the higher voltage source, a higher voltage source voltage is outputted to a detection output terminal, while the voltage at the detection terminal is greater than or equal to the predetermined factor times the voltage of the higher voltage source, a lower voltage source voltage is outputted to the detection output terminal.

Abstract: A first control switch is connected between a first terminal to which one terminal of a first boosting capacitor element is connected and a supply node of an input voltage. A second control switch is connected between a second terminal to which the other terminal of the first boosting capacitor element is connected and the supply node of the input voltage. A first switch element is connected between a third terminal to which one terminal of a second boosting capacitor element is connected and at which an output voltage is generated and the first terminal. A second switch element is connected between a node of a reference voltage side of the input voltage and the second terminal. A control circuit detects the output voltage and controls the first and second control switches to obtain the desired output voltage on the basis of a detection result.

Abstract: According to one embodiment, a hysteresis comparator is provided with to first to third current sources, a comparison amplifying unit, a reference voltage generating unit, a current mirror circuit, first to fifth N-channel MOS transistors, and first to fifth terminals.

Abstract: According to an embodiment, the threshold value generation unit generates a setting voltage and converts the setting voltage to a first current. One end of the first resistor is connected to a detection terminal. When a voltage applied to the detection terminal is greater than or equal to a predetermined factor times the voltage of the higher voltage source, the detection unit causes a constant detection terminal input current to flow from the detection terminal to the first resistor. When the voltage at the detection terminal is less than the predetermined factor times the voltage of the higher voltage source, a higher voltage source voltage is outputted to a detection output terminal, while the voltage at the detection terminal is greater than or equal to the predetermined factor times the voltage of the higher voltage source, a lower voltage source voltage is outputted to the detection output terminal.

Abstract: According to one embodiment, a hysteresis comparator is provided with to first to third current sources, a comparison amplifying unit, a reference voltage generating unit, a current mirror circuit, first to fifth N-channel MOS transistors, and first to fifth terminals.

Abstract: According to an aspect of the present invention, there is provided an output circuit including a first output unit supplying a first voltage, a second output unit supplying a second voltage, a switching unit selectively outputting, to an output end, the first voltage from the first output unit and the second voltage from the second output unit, a detection unit detecting a voltage of the output end, and a control unit controlling one of the first voltage and the second voltage on the basis of the voltage detected by the detection unit.

Abstract: An output buffer circuit is provided that outputs an input signal output from a circuit operating at a first power supply voltage to another circuit operating at a second power supply voltage higher than the first power supply voltage. The output buffer circuit includes an output driver circuit including a pull-up transistor and a pull-down transistor connected between the second power supply voltage and a reference voltage. A first driving circuit outputs a first control signal to control the pull-down transistor. A second driving circuit includes a latch circuit to latch signals and outputs a second control signal to control the pull-up transistor based on retained data in that latch circuit. A level shifter changes the retained data in the latch circuit when logic of the input signal changes.

Abstract: An output buffer circuit is provided that outputs an input signal output from a circuit operating at a first power supply voltage to another circuit operating at a second power supply voltage higher than the first power supply voltage. The output buffer circuit includes an output driver circuit including a pull-up transistor and a pull-down transistor connected between the second power supply voltage and a reference voltage. A first driving circuit outputs a first control signal to control the pull-down transistor. A second driving circuit includes a latch circuit to latch signals and outputs a second control signal to control the pull-up transistor based on retained data in that latch circuit. A level shifter changes the retained data in the latch circuit when logic of the input signal changes.

Abstract: A first control switch is connected between a first terminal to which one terminal of a first boosting capacitor element is connected and a supply node of an input voltage. A second control switch is connected between a second terminal to which the other terminal of the first boosting capacitor element is connected and the supply node of the input voltage. A first switch element is connected between a third terminal to which one terminal of a second boosting capacitor element is connected and at which an output voltage is generated and the first terminal. A second switch element is connected between a node of a reference voltage side of the input voltage and the second terminal. A control circuit detects the output voltage and controls the first and second control switches to obtain the desired output voltage on the basis of a detection result.

Abstract: According to an aspect of the present invention, there is provided an output circuit including a first output unit supplying a first voltage, a second output unit supplying a second voltage, a switching unit selectively outputting, to an output end, the first voltage from the first output unit and the second voltage from the second output unit, a detection unit detecting a voltage of the output end, and a control unit controlling one of the first voltage and the second voltage on the basis of the voltage detected by the detection unit.

Abstract: When a time code signal corresponding to an image signal, to which a format conversion changing the number of frames per second is executed, is transmitted, information indicating a frame position where image data is changed through the format conversion in the image signal is attached to the time code signal to be transmitted. Alternatively, information indicating a synchronous state between frame conversion cycles in the format conversion and time code progression is attached to the time code signal. In the foregoing manner, a relationship between the frame position and the time code can be accurately grasped. Further, a secondary conversion (inverse conversion) is accurately executed to the image signal by means of the time code signal.

Abstract: A video signal recording and reproduction device of this invention uses one of a plurality of terminals for receiving input of component video signal to also serve as a composite video signal input terminal, thereby reducing a number of the input terminals. This realizes a reduction in size of the device, yet maintains the device to be capable of receiving both inputs of component video signal and composite video signal. The video signal recording and reproduction device of this invention also uses one of a plurality of terminals for outputting component video signal to also serve as a composite video signal output terminal, thereby reducing a number of the output terminals. This realizes a further reduction in size of the device, yet maintains the device to be capable of providing both outputs of component video signal and composite video signal.

Abstract: The present invention comprises the step of reading a check-receiving data included in a transmitted time code signal and using the read check-receiving data to generate a transmitting side checking data, and the step of attaching the transmitting side checking data to the transmitted time code signal, as a pre-processing step at the time of transmitting the time code signal. The present invention comprises the step of reading the check-receiving data from the received time code signal and using the read check-receiving data to generate a receiving side checking data, and the step of reading the transmitting side checking data from the received time code signal and comparing the read transmitting side checking data to the receiving side checking data, thereby verifying whether or not an error is generated in the received time code signal. In this way, an error can be detected in the time code signal, as a post-processing step after the time code signal is received.

Abstract: A semiconductor integrated circuit includes first and second differential amplification devices to amplify a voltage difference of input signals inputted from a positive input terminal and a negative input terminal, first and second addition devices to add an output of the first differential amplification device and the output of the second differential amplification device, an output stage control device controlled by the first and second addition devices, and output stage controlled by the output stage control device, and an output terminal connected to the output stage.

Abstract: When a time code signal corresponding to an image signal, to which a format conversion changing the number of frames per second is executed, is transmitted, information indicating a frame position where image data is changed through the format conversion in the image signal is attached to the time code signal to be transmitted. Alternatively, information indicating a synchronous state between frame conversion cycles in the format conversion and time code progression is attached to the time code signal. In the fore going manner, a relationship between the frame position and the time code can be accurately grasped. Further, a secondary conversion (inverse conversion) is accurately executed to the image signal by means of the time code signal.

Abstract: A semiconductor integrated circuit includes first and second differential amplification devices to amplify a voltage difference of input signals inputted from a positive input terminal and a negative input terminal, first and second addition devices to add an output of the first differential amplification device and an output of the first differential amplification, an output stage control device controlled by the first and second addition devices, an output stage controlled by the output stage control device, and an output terminal connected to the output stage.

Abstract: The chip size of the high breakdown voltage push-pull output circuit for the semiconductor device can be reduced by use of only the low breakdown voltage transistor elements. Between the voltage supply terminal HVCC and the ground terminal GND, the control transistor element (Q1) and the voltage transistor element (Q3) are connected in series and stacked vertically. In the same way, the voltage transistor element (Q4) and the control transistor element (Q2) are connected in series and stacked vertically. Further, the output terminal (OUT) is derived from between the voltage transistor element (Q3) and the voltage transistor element (Q4). The supply voltage of 12V supplied through the voltage supply terminal HVCC is divided as voltages of 6V by the bias circuit BI, and then supplied to the bases of the two voltage transistor elements (Q3 and Q4), respectively. When the output is low, the supply voltage of 12V is divided 1/2 by the control transistor element (Q1) and the voltage transistor element (Q3).

Abstract: A CMOS level converter including two CMOS inverter that are complimentary coupled with each other. Each of the CMOS inverter includes two MOS transistors and is coupled between a source voltage and a ground potential in series. When an input signal begins to change from a low level to a high level, one of the MOS transistors in an input side CMOS inverter is turned off, and the inverter is coupled through a diode to the ground potential. As the input level rises gradually, on the input side inverter, due to a high level output from an output side inverter, the MOS transistor turns on. As a consequent, the output is set at the ground potential in the level conversion, even when the amplitude is insufficient.

Abstract: A low-voltage output circuit has the first and the second MOS transistors. An input signal is fed to the gate of the first transistor. Either of the source and the drain of the first transistor is supplied with a predetermined potential. The other is connected to an output terminal and generates an output signal. The first transistor raises the output signal to the predetermined potential level in response to the input signal. Either of the source and the drain of the second MOS transistor is connected to the gate of the first transistor. The other is connected to the output terminal. The circuit further includes a device for supplying a bias voltage to a gate of the second transistor so that the first and second transistors remain turned off at different gate bias potentials and the second transistor turns on before the first transistor when the output signal is raised to the predetermined potential level to keep the first transistor remaining turned off.

Abstract: An output circuit has a bipolar transistor circuit of a 1st and a 2nd bipolar transistor connected in Darlington configuration. The base of the 1st transistor is supplied with an input signal. The collector of the 2nd transistor is connected to a power supply through a 1st diode. And, a signal is outputted from the emitter of the 2nd transistor. The output circuit also includes a 1st PMOS transistor. The source of the 1st PMOS transistor is connected to the base of the 2nd transistor, its drain being grounded, and its the backgate being connected to the power supply through the 1st diode. The output circuit may further includes a 2nd PMOS transistor having a source and a backgate both connected to the power supply, a drain connected to the base of the 2nd transistor through a second diode, and a gate supplied with an inverting signal of the input signal.