Abstract: In an output circuit, a signal /.phi. opposite in phase to a signal /EN inputted through an input terminal 3 is generated by an inverter 1, and a signal .phi. in phase with the signal /EN is generated by two inverters 8 and 2. When the input signal /EN changes from a high level to a low level, a bipolar NPN transistor 35 is turned on instantaneously to decide an output terminal 5 at the low level forcedly. On the other hand, when the signal /EN changes from the low level to the high level, an NPN transistor 10 is turned on in advance of the other circuits to decide the output terminal 5 at the high level forcedly. Accordingly, it is possible to roughly equalize a delay time (from when the level of the input signal /EN changes at the input terminal 3 to when the level of the signal /.phi. changes at an output terminal 4) to another delay time (to when the level of the signal .phi. changes at the output terminal 5), thus realizing an ideal phase relationship between the two signals/.phi. and .phi.

Abstract: A driver circuit suitable for use to secure output characteristics higher than the element breakdown voltage in an output circuit. The driver circuit includes first and second switching elements connected between a first supply voltage and an outward terminal for driving a load, a relaxation voltage applying section for applying a voltage lower than the first supply voltage to a junction point between the first and second switching elements and a back gate of the second switching element, and a control section for turning on the second switching element and then the first switching element in sequence when the driver circuit is turned on, and turning off the first switching element and then the second switching element in sequence when the driver circuit is turned off.

Abstract: It is an object of this invention to provide a novel network interface system which is able to connect automatically to the respective network stations having different data transfer speeds, in order to avoid the above problems. According to this invention, there is provided a detector and a selector in the communication interface to automatically select the appropriate data transfer speed. In the above structure, the speed of communication data transferred by a network is one of two detected by the detector which is able to detect a transfer speed and provide outputs at a first level signal when the transfer speed is at one level and outputs a second level signal when it is at a second level. The selecting means selects the frequency to connect a network station in response to the signal output from the detector. As a result, users need not select the module by themselves, the system automatically select the module.

Abstract: A phase comparator has a switching circuit controlled by a switch signal and a phase comparing unit. The switching circuit receives a reference pulse signal having a duty ratio of 50% and a reception data signal having a duty ratio of less than 50%. One of these signals is selected by the switching circuit on the basis of control of the switch signal. The selected signal and an output signal from a voltage-controlled oscillator are supplied to the phase comparing unit. The phase comparing unit compares phases of the two signals. When the phase of the output signal from the voltage-controlled oscillator lags behind the phase of the selected reference pulse signal or reception data signal, the phase comparing unit outputs a first pulse signal, having a width corresponding to a phase difference between the two signals, for advancing the phase of the output signal from the voltage-controlled oscillator.

Abstract: An output circuit for obtaining stable rising and falling characteristics regardless of variations in threshold voltages of output transistors. The output circuit obtains such favorable characteristics by using input signals changing in a complementary manner, a first MOS transistor which outputs a high potential level signal in response to a drive signal, and an output terminal for receiving the high potential level signal. In addition, the output circuit contains a drain-current control connected to a gate-source path for maintaining a drain current at a predetermined value, a second MOS transistor connected to a gate-source path which sets the output terminal at a ground level when it is turned on, and a second drain current control connected to a gate source of the second MOS transistor for maintaining a drain current at a predetermined value.

Abstract: A first Schottky barrier type NPN transistor for pulling up an output signal and a second Schottky barrier type NPN transistor for pulling down an output signal are connected, in a totem pole configuration, between the nodes of power source potential and ground potential, a connecting point of these NPN transistors is connected to an output terminal. A resistor and a Schottky diode are connected in series between the node of the power source potential and the collector of the first NPN transistor. The collector of a third Schottky barrier type NPN transistor for driving the first NPN transistor is connected to a connecting point of the resistor and the Schottky diode, and the emitter of the third NPN transistor is connected to the base of the first NPN transistor. A resistor is connected between the base and emitter of the first NPN transistor.

Abstract: A level shift circuit of the present invention includes an input differential pair of transistors, as an input circuit section, which are switchingly operated in accordance with the level of an input signal supplied from a preceding circuit. An output circuit section is composed of first and second emitter follower transistors. A third transistor has its current path connected at one end to an emitter of the first emitter follower transistor and makes an output level of the first emitter follower transistor at a predetermined level. A fourth transistor has its current path connected at one end to the other end of the reference potential and its gate electrode connected to an output terminal of the second emitter follower transistor and is driven by an output voltage of the second emitter follower transistor to allow an output level of the first emitter follower transistor to be shifted to a low level.

Abstract: Disclosed herein is a signal output circuit designed for use in a CMOS IC and having a bipolar transistor at output. A high-level output NPN-type bipolar transistor has its collector-emitter path connected between a node to which a high-level power-supply potential is applied, and an output node for outputting a signal. A low-level output NPN-type bipolar transistor has its collector-emitter path connected between the output node and a node to which a low-level power-supply potential is applied. An N-channel MOS transistor has its source-drain path connected between the output node and the base of the bipolar transistor, and is controlled by a first input signal. An N-channel MOS transistor has its source-drain path connected between the output node and the node to which the low-level power-potential is applied.

Abstract: In an output circuit having pull down and pull up npn transistors, a static output-current control circuit is provided. The control circuit is turned on by detecting that a potential at the output terminal of the circuit is at a predetermined value of less. When the input signal supplied to the input terminal goes from CMOS level "0" to CMOS level "1" to change the voltage at the output terminal from TTL level "1" to TTL level "0", and when the potential at the output terminal becomes a predetermined value or less, the static output-current control circuit is turned on. A base current is supplied from the static output-current control circuit to the pull down npn transistor. As a result, the static output current is not decreased but kept constant.

Abstract: Disclosed herein is a Bi-MOS logic circuit comprising first and second NPN transistors forming an output buffer; first and second MOS transistors for controlling the NPN transistors when the logic circuit is set to a data-latching mode; and third and fourth MOS transistors for controlling the NPN transistors when the logic circuit is set to a data-inputting mode. The Bi-MOS logic circuit further comprises a switch circuit for discharging a parasitic capacitor located at the node of the series circuit comprised of the first and second MOS transistors.

Abstract: There is provided an improved output circuit having high speed operation and low power dissipation. The circuit having MOS pull up and pull down transistors, wherein a control signal to the pull down MOS is delayed to discharge parasitic capacitance and to prevent both MOS transistors from being on simultaneously.

Abstract: A complementary signal output circuit for supplying an in-phase and an anti-phase output signal in response to an input signal. The falling of the in-phase signal from a high to a low level and the rising of the anti-phase signal from a low to a high level are both controlled in a manner which serves to speed up the output of the anti-phase signal and reduce skew between the complementary signals. This is accomplished by providing a number of inverter means, and transistor means which outputs a low-to-high signal to the anti-phase output in response to the inverted input signal. Additional circuitry responsive to the input signal is used to prevent undesired current from flowing through the transistor and inverter means.

Abstract: An output circuit provides a high voltage output signal in response to a low voltage input signal. The output circuit includes a pull-up transistor for raising the output signal substantially to a power source voltage level and a pull-down transistor responsive to the input signal for lowering the output signal substantially to the ground level. The pull-up transistor is biased by a self-bias circuit triggered by a prescribed level of a control signal. The self-bias circuit continues to bias the pull-up MOS transistor in order to bring the output signal level to the high voltage level, even if the prescribed level period of the control signal terminates.

Abstract: To obtain a logic result output signal with a gentle leading edge at high response speed, the logic circuit comprises an input section for receiving at least one input signal to find a logic result signal; a control section including at least one first transistor, having a constant collector load connected between the collector thereof and a supply voltage, turned on or off in response to the logic result signal to generate a control signal; an output section including at least two second and third transistors turned on or off alternatively in response to the control signal to generate a logic output signal; and a variable resistance circuit connected in parallel to the constant collector load, for increasing the resistance of the collector load (i.e. time constant at the collector) with increasing collector potential of the first transistor. The variable resistance circuit includes diodes connected in series or a transistor.

Abstract: A totem pole type output buffer section comprises a pull-up NPN bipolar transistor and a pull-down NPN bipolar transistor. These NPN bipolar transistors are selectively switch-controlled by a first MOS FET. Another NPN bipolar transistor is darlington-connected to the pull-down NPN bipolar transistor, and is switch-controlled by the second MOS FET. The second MOS FET is of the same conductivity type as and has a gate connected to a gate of the first MOS FET.

Abstract: A logic circuit comprises a current control means including first and second MOS transistors for controlling the current to the output circuit and also for controlling the output wave form, in accordance with the input signal and the output signal. When the output signal rises from a low level to a high level, a large current is supplied to the output circuit to get a steep rise. When the output signal is high level, the current to the output circuit becomes small, and the power consumption is reduced.

Abstract: A logic circuit comprises an input section for inputting a signal and outputting an output signal through a CMOS inverter circuit; an output section having first darlington-connected bipolar transistors and a bipolar transistor to the first bipolar transistors in the shape of a totem pole, and outputting a logic signal with respect to the input signal based on the operations of the first and second bipolar transistors; and a control section having CMOS transistors operated on the basis of the ouptut signal of the input section, and controlling the operations of the first and second bipolar transistors of the output section through the CMOS transistors in accordance with the output signal of the input section.

Abstract: A tri-state output circuit comprising an input section having complementary field effect transistors which constitute NOR gate and investor circuits, a control section having first and second current control circuits, and an output section having bipolar transistors wherein an input signal and a tri-state signal are logically processed in the input section and its result applied to the control section. Then, the switching operations of the output section and a high impedance condition of the output terminal of the tri-state output circuit are controlled by the control section consisting of a plurality of complementary FETs, thereby achieving a low power consumption, a high load driving capability, and a high speed operation.

Abstract: A buffer circuit comprises first to third CMOS inverters whose input terminals are mutually connected, first and second npn transistors whose bases are commonly connected to an output terminal of the first CMOS inverter and whose emitters are respectively connected to output terminals of the second and third CMOS inverters, fourth and fifth CMOS inverters for inverting the output signals of the first and third CMOS inverters, a third npn transistor whose base and emitter are respectively connected to output terminals of the fourth and fifth CMOS inverters, fourth and fifth npn transistors whose conduction states are controlled by the output signals of the first and fourth CMOS inverters, first and second n-channel MOS transistors which are serially connected to the fourth and fifth npn transistors, respectively, and whose gates are respectively connected to the third and fifth CMOS inverters, and third and fourth n-channel MOS transistors which are respectively connected between the gates of the first and sec