Abstract: According to one embodiment, a display element includes a plurality of scanning lines and a plurality of signal lines. Into the plurality of signal lines, signals of different polarities are alternately input, respectively. In the respective regions surrounded by the scanning lines and the signal lines, a first pixel and a second pixel are arrayed. Along the scanning line, two each of the first pixels and the second pixels are provided, and the two first pixels or the two second pixels are arrayed so as to be juxtaposed to each other. Along the signal line, the first pixel and the second pixel are arrayed alternately.

Abstract: According to one embodiment, liquid crystal display device includes an array substrate, a counter substrate, and a liquid crystal layer. The array substrate includes a plurality of pixel electrodes, a plurality of gate lines, a plurality of source lines, a plurality of switching elements, and a plurality of light shielding layers. Each of the light shielding layers extends to cross, among the source lines, even-numbered source lines arranged in the direction of the extension of the gate lines.

Abstract: According to one embodiment, a device includes a first substrate including a gate line, a source line which extends to intersect with the gate line, a pixel electrode which includes a primary pixel electrode extending substantially parallel to the source line, and a switching element located at the intersection of the gate line and the source line, a second substrate includes a common electrode which extends substantially parallel to the primary pixel electrode on both sides across the primary pixel electrode, and a liquid crystal layer including liquid crystal molecules held between the first and second substrates. The switching element includes a drain line which is electrically connected to the pixel electrode and which is located to overlap the gate line.

Abstract: A liquid crystal display device using a pseudo-dot inversion driving system includes a pixel circuit arranged in a matrix shape in a row direction and a column direction. First and second gate lines extend in the row direction. First and second signal lines extend in the column direction. The pixel circuit includes a pixel electrode arranged between the first and second signal lines and electrically connected with the first signal line through a switching element. Parasitic capacitance formed between the pixel electrode and the first signal line is smaller than the parasitic capacitance between the pixel electrode and the second signal line.

Abstract: In an array substrate, a first pixel is arranged at one end of an active area, and a second pixel is arranged adjacent to the first pixel more inside of the active area than the first pixel. A common electrode extends to the first and second pixels, and an insulating layer is formed on the common electrode. First and second pixel electrodes are formed on the insulating layer in the first and second pixels. The pixel electrodes include electrode portions forming slits facing the common electrode. A second substrate includes a shield layer arranged outside the active area. The first pixel electrode is formed more widely than the second pixel electrode, and extends to outside of the active area. The first pixel electrode includes an extending portion extending to outside of the active area and facing the shield layer.

Abstract: A first semiconductor layer is formed in the shape of an island in an active area displaying images on an array substrate. A second semiconductor layer is formed in the shape of an island outside the active area. A first insulating film covers the first and second semiconductor layers. A gate line is formed on the first insulating film and extends in a first direction. The gate line includes a gate electrode crossing the first semiconductor layer and a crossing portion crossing the second semiconductor layer. A second insulating film covers the gate line. A source line is formed on the second insulating film and extends in a second direction. The source line includes a source electrode contacting with the first semiconductor layer. A drain electrode is formed on the second insulating film apart from the source line and contacting with the first semiconductor layer.

Abstract: According to one embodiment, a liquid crystal display device includes, a first substrate including a switching element which is electrically connected to a gate line and a source line and includes a drain electrode opposed to a storage capacitance line, a pixel electrode which includes a main pixel electrode extending in a second direction and a sub-pixel electrode which extends in a first direction at a position inside a position above an edge of the drain electrode and is put in contact with the drain electrode, a second substrate including a common electrode, and a liquid crystal layer.

Abstract: A first substrate includes first and second gate lines extending in a first direction. First, second, and third source lines respectively extend in a second direction orthogonally crossing the first direction and crossing the first and second gate lines. A first pixel electrode is arranged adjoining the first source line and extends in the second direction. A second pixel electrode is arranged adjoining the third source line and extends in the second direction. A second substrate includes a common electrode arranged above the second source line extending in the second direction between the first source line and the third source line. The first and second source lines, the first and second gate lines, and the first pixel electrode form a first pixel, and the second and the third source lines, the first and second gate lines, and the second pixel electrode form a second pixel.

Abstract: According to one embodiment, a device includes a first substrate including a gate line, a source line which extends to intersect with the gate line, a pixel electrode which includes a primary pixel electrode extending substantially parallel to the source line, and a switching element located at the intersection of the gate line and the source line, a second substrate includes a common electrode which extends substantially parallel to the primary pixel electrode on both sides across the primary pixel electrode, and a liquid crystal layer including liquid crystal molecules held between the first and second substrates. The switching element includes a drain line which is electrically connected to the pixel electrode and which is located to overlap the gate line.

Abstract: A signal line drive circuit according to the present invention has: a latch circuit which latches digital pixel data; a D/A converter which converts a latch output from the latch circuit into an analog video signal; an AMP which amplifies the analog video signal converted by the D/A converter; and a signal selection circuit which selects a signal line to which the analog video signal amplified by the AMP is supplied. The AMP has: an odd number of inverters which are cascade-connected; capacitor elements which are respectively connected between stages of the inverters and between an input terminal of the inverter on a first stage and an output terminal of the inverter on a last stage; a first power supply line which supplies a power supply voltage to the inverter on the first stage; and a second power supply line which supplies a power supply voltage to inverters other than the inverter on the first stage.

Abstract: In order to reduce the scale of drive ICs and to prevent uneven display in signal line selective drive, in this liquid crystal display device, for each group in which one video output line corresponds to N signal lines, the signal line is switched and connected to the video output line via an analog switch ASW. Thus, the number of the video output lines is reduced to 1/N. Moreover, as to an Lth scan line, for each of the groups, a signal line to which a video signal having its polarity inverted between an L-1th scan line and the Lth scan line is supplied is selected first and a signal line to which a video signal having its polarity not inverted is supplied is selected later. Thus, a video signal in which a polarity is not inverted and no potential change occurs is supplied to the signal line later.

Abstract: A signal line drive circuit according to the present invention has: a latch circuit which latches digital pixel data; a D/A converter which converts a latch output from the latch circuit into an analog video signal; an AMP which amplifies the analog video signal converted by the D/A converter; and a signal selection circuit which selects a signal line to which the analog video signal amplified by the AMP is supplied. The AMP has: an odd number of inverters which are cascade-connected; capacitor elements which are respectively connected between stages of the inverters and between an input terminal of the inverter on a first stage and an output terminal of the inverter on a last stage; a first power supply line which supplies a power supply voltage to the inverter on the first stage; and a second power supply line which supplies a power supply voltage to inverters other than the inverter on the first stage.

Abstract: In forward direction pulse shift, by turning off a sixteenth transistor, a through-current is prevented from flowing between the fifth transistor and the seventh transistor. In backward direction pulse shift, by turning off the fifteenth transistor, a through-current is prevented from flowing between the fifth and sixth transistors. Thus, a potential variation in an output signal of a shift register between the forward direction pulse shift and the backward direction pulse shift is prevented.

Abstract: A signal line drive circuit according to the present invention has: a latch circuit which latches digital pixel data; a D/A converter which converts a latch output from the latch circuit into an analog video signal; an AMP which amplifies the analog video signal converted by the D/A converter; and a signal selection circuit which selects a signal line to which the analog video signal amplified by the AMP is supplied. The AMP has: an odd number of inverters which are cascade-connected; capacitor elements which are respectively connected between stages of the inverters and between an input terminal of the inverter on a first stage and an output terminal of the inverter on a last stage; a first power supply line which supplies a power supply voltage to the inverter on the first stage; and a second power supply line which supplies a power supply voltage to inverters other than the inverter on the first stage.

Abstract: In order to improve display quality, a liquid crystal display device includes a video signal supply line for supplying a video signal to signal lines, and a signal line drive circuit which sequentially turns on analog switches connected between the video signal supply line and each signal line. The video signal supply line is branched into a plurality of lines, and the analog switches are connected to the branched video signal supply lines in a distributed manner. The signal line drive circuit consecutively turns on the analog switches connected to different branched video signal supply lines.

Abstract: With regard to a display device having an SRAM incorporated in a pixel, a technology is disclosed, which is capable of reducing manufacturing costs by simplifying a constitution of a driver. A write voltage equivalent to white or black represented by a tone level of a normal display area is converted into a write voltage corresponding to a brightest white display or a darkest black display in the pixel, and is held in the SRAM of each pixel. In the case of normal display, display is carried out with the write voltage represented by the tone level of the normal display area. In the case of static image display, display is carried out with the write voltage corresponding to the brightest white display or the darkest black display in the pixel, the write voltage being held in the SRAM. Since the normal display and the static image display can be carried out with a write voltage supplied from one driver, the constitution of the driver can be simplified.

Abstract: In order to reduce the scale of drive ICs and to prevent uneven display in signal line selective drive, in this liquid crystal display device, for each group in which one video output line corresponds to N signal lines, the signal line is switched and connected to the video output line via an analog switch ASW. Thus, the number of the video output lines is reduced to 1/N. Moreover, as to an Lth scan line, for each of the groups, a signal line to which a video signal having its polarity inverted between an L-1th scan line and the Lth scan line is supplied is selected first and a signal line to which a video signal having its polarity not inverted is supplied is selected later. Thus, a video signal in which a polarity is not inverted and no potential change occurs is supplied to the signal line later.

Abstract: In forward direction pulse shift, by turning off a sixteenth transistor, a through-current is prevented from flowing between the fifth transistor and the seventh transistor. In backward direction pulse shift, by turning off the fifteenth transistor, a through-current is prevented from flowing between the fifth and sixth transistors. Thus, a potential variation in an output signal of a shift register between the forward direction pulse shift and the backward direction pulse shift is prevented.

Abstract: A liquid crystal display realizes high resolution without enlarging a frame area of an array substrate in the display. The display connects analog switch pairs each consisting of a p-TFT and an n-TFT to signal lines, respectively. Among the TFTs, those having the same polarity and connected to adjacent signal lines are provided with drain electrodes that are connected to a video bus through a common contact hole. Sharing the contact holes among the TFTs enables the switch pairs to be juxtaposed at fine pixel pitches.

Abstract: A signal line drive circuit according to the present invention has: a latch circuit which latches digital pixel data; a D/A converter which converts a latch output from the latch circuit into an analog video signal; an AMP which amplifies the analog video signal converted by the D/A converter; and a signal selection circuit which selects a signal line to which the analog video signal amplified by the AMP is supplied. The AMP has: an odd number of inverters which are cascade-connected; capacitor elements which are respectively connected between stages of the inverters and between an input terminal of the inverter on a first stage and an output terminal of the inverter on a last stage; a first power supply line which supplies a power supply voltage to the inverter on the first stage; and a second power supply line which supplies a power supply voltage to inverters other than the inverter on the first stage.