Abstract: A circuit block operates while receiving a clock from an external circuit. A load balance circuit is connected to a shared power supply terminal together with the circuit block, and provides predetermined power consumption. A clock detection unit detects input of the clock from an external circuit. When the clock detection unit detects stopping of input of the clock, the load balance circuit is switched to the active state.

Abstract: A variable delay circuit has a simple configuration for being incorporated in a timing generator to control a delay time in real time and assure a timing margin. The variable delay circuit of the timing generator includes a delay circuit having a plurality of cascaded clock buffers; a plurality of cascaded data buffers; and data holding circuits for outputting data to the data buffers in accordance with the clock from the delay circuit. The delay amount added to the data by the data buffers is made identical to the delay amount added to the clock by the clock buffers.

Abstract: A variable delay circuit applies a variable delay that corresponds to an analog signal to a reference clock so as to generate a delayed clock. A phase detection unit detects the phase difference between the delayed clock and the reference clock, and generates a phase difference signal having a level that corresponds to the phase difference. A counter performs a counting up operation or a counting down operation according to the level of the phase difference signal. A digital/analog converter converts the count value of the counter into an analog signal, and supplies the count value thus converted to the variable delay circuit.

Abstract: Provided is a test apparatus, including a storage section that stores a count value for adjusting a phase of a sampling clock indicating a timing of acquiring an output signal of a DUT; a clock generating section that generates the sampling clock indicating the timing of acquiring the output signal, based on an offset corresponding to the count value and on a reference clock; a first delay section that outputs a first delay clock having a frequency equal to the frequency of the sampling clock and a preset phase difference in relation to the sampling clock, based on the reference clock and the offset; a phase detecting section that detects a phase difference between the first delay clock and a transition point of the output signal, and changes the count value in a direction that decreases the phase difference; a timing comparison section that acquires the output signal according to a transition timing of the sampling clock; and a judging section that judges acceptability of the acquired output signal by compar

Abstract: Provided is an oscillation circuit for generating an oscillation signal synchronized with a supplied reference clock, including: a voltage control oscillation section that, when triggered by each edge of the reference clock, stops oscillation of the oscillation signal having a frequency in accordance with a supplied control voltage to start new oscillation; a phase comparing section that compares a phase of a comparison signal that is in accordance with the oscillation signal outputted from the voltage control oscillation section and a phase of a signal that is in accordance with the reference clock; and a voltage control section that supplies the control voltage in accordance with a comparison result of the phase comparing section, to the voltage control oscillation section.

Abstract: A ring oscillator oscillates at a frequency determined by an input bias signal. A bias signal adjusting unit produces a bias signal for the ring oscillator using feedback so that the oscillation frequency of the ring oscillator matches a predetermined reference frequency. An individual bias circuit includes a plurality of bias circuits provided for a total of N second variable delay elements, respectively. The bias circuits are configured such that the bias signals can be individually adjusted.

Abstract: Provided is a load fluctuation compensation circuit for compensating a power source voltage supplied to an operation circuit, the load fluctuation compensation circuit including: a periodic signal changing section that receives a power source voltage from a power source shared with the operation circuit, and outputs a changed signal resulting from changing a supplied periodic signal according to the power source voltage; a phase comparator that compares a phase of the periodic signal with a phase of the changed signal outputted from the periodic signal changing section; an initializing section that generates a bias voltage supplied to the periodic signal changing section and adjusts a phase difference between the periodic signal and the changed signal to a preset value, based on the comparison result of the phase comparator; a controller that holds the bias voltage outputted from the initializing section when the phase difference between the periodic signal and the changed signal has become the preset value;

Abstract: Provided is a load fluctuation compensation circuit, including a first delay circuitry section that delays a clock signal supplied thereto by a delay amount that fluctuates by a prescribed first fluctuation amount in relation to a unit fluctuation amount of a power supply voltage supplied to a performance circuit; a second delay circuitry section that is disposed in parallel with the first delay circuitry section and that delays the clock signal supplied thereto by a delay amount that fluctuates by a second fluctuation amount, which is greater than the first fluctuation amount, in relation to the unit fluctuation amount of the power supply voltage supplied to the performance circuit; a load circuit that is connected to a common power supply wiring in parallel with the performance circuit; and a phase detecting section that detects a phase difference between the clock signal output by the first delay circuitry section and the clock signal output by the second delay circuitry section and that controls an amount

Abstract: Provided is a variable delay circuit outputting an output signal delayed with respect to an input signal by a designated delay time, including: a delay controller outputting a control voltage according to the delay time; a MOS transistor receiving the control voltage at a gate, and outputs a drain current according to the control voltage; a correction section connected in parallel to a source and a drain of the current controlling MOS transistor, and outputs a correction current on a monotonic decrease as the drain current increases in a range larger than a predetermined boundary current within a normal usage range of the drain current; and a delay element running an output current resulting from adding the correction current to the drain current, between the delay element and an output terminal of the variable delay circuit, in changing a signal value of the output signal according to the input signal.

Abstract: To provide a load fluctuation correction circuit having a function of correcting the change in the current consumption amount due to the change in the driving state of a logic circuit, thereby suppressing the change in the source voltage applied to the logic circuit.

Abstract: Provided is a test apparatus that tests fluctuation of a power supply voltage supplied to a device under test, including an oscillator that outputs a clock signal having a frequency that corresponds to the power supply voltage supplied to the power supply input terminal of the device under test, and a measuring section that measures the frequency of the clock signal. For example, the oscillator outputs as the clock signal an output signal of any one negative logic element from among an odd number of negative logic elements connected in a loop, and at least one of the negative logic elements operates using, as a voltage source, a voltage corresponding to the power supply voltage supplied to the power supply input terminal of the device under test.

Abstract: A variable delay circuit has a simple configuration for being incorporated in a timing generator to control a delay time in real time and assure a timing margin. The variable delay circuit of the timing generator includes a delay circuit having a plurality of cascaded clock buffers; a plurality of cascaded data buffers; and data holding circuits for outputting data to the data buffers in accordance with the clock from the delay circuit. The delay amount added to the data by the data buffers is made identical to the delay amount added to the clock by the clock buffers.

Abstract: Provided is a load fluctuation compensation circuit for compensating a power source voltage supplied to an operation circuit, the load fluctuation compensation circuit including: a periodic signal changing section that receives a power source voltage from a power source shared with the operation circuit, and outputs a changed signal resulting from changing a supplied periodic signal according to the power source voltage; a phase comparator that compares a phase of the periodic signal with a phase of the changed signal outputted from the periodic signal changing section; an initializing section that generates a bias voltage supplied to the periodic signal changing section and adjusts a phase difference between the periodic signal and the changed signal to a preset value, based on the comparison result of the phase comparator; a controller that holds the bias voltage outputted from the initializing section when the phase difference between the periodic signal and the changed signal has become the preset value;

Abstract: A timing generator that needs no analog circuit for adding jitters and allows the circuit scale and power consumption to be reduced.

Abstract: The accuracy of the delay amount to be imparted to a timing signal is improved by increasing the delay amount obtained by a first stage of a delay element. A variable delay 50 which comprises a DA converter 51 which supplies current 51 based on delay setting data; a delay element 53 which imparts a delay amount Tpd to a prescribed signal and outputs the signal; and a bias circuit 52 which is connected such that the amount of current flown in the DA converter 51 and the amount of current flown in the delay element 53 become equal, wherein the DA converter 51 allows the relationship between the delay setting data DATA and the current Id to be hyperbolic (inversely proportional). As a result, the relationship between the delay setting data DATA and the delay amount Tpd can be linear, whereby the delay amount obtained by a first stage of the delay element can be widened.

Abstract: Provided is a test apparatus for testing a device under test, the test apparatus including: a pattern generating section that inputs a test pattern to the device under test; a judging section that judges whether the device under test is defective or not, based on an output signal outputted from the device under test; a power supply apparatus that supplies a source power to the device under test; and a setting section that detects a fluctuation amount of the source voltage resulting when the test pattern is inputted to the device under test, and sets, based on the detected fluctuation amount, a current range within which a compensation current that is in accordance with a fluctuation of a consumption current consumed by the device under test is generated at a predetermined number of levels so as to compensate a fluctuation of a source voltage to be applied to the device under test attributable to the fluctuation of the consumption current.

Abstract: A ring oscillator oscillates at a frequency determined by an input bias signal. A bias signal adjusting unit produces a bias signal for the ring oscillator using feedback so that the oscillation frequency of the ring oscillator matches a predetermined reference frequency. An individual bias circuit includes a plurality of bias circuits provided for a total of N second variable delay elements, respectively. The bias circuits are configured such that the bias signals can be individually adjusted.

Abstract: There is provided a signal output apparatus for outputting a pattern signal. The signal output apparatus includes a pattern generating section that generates waveform data of the pattern signal to be generated, a timing generating section that generates timing signals in accordance with an expected pattern cycle time of the pattern signal, a timing control section that receives the waveform data output from the pattern generating section, and controls output timings of the timing signals to be output from the timing generating section, in accordance with the waveform data, and a waveform shaping section that generates the pattern signal corresponding to data values of the waveform data output from the pattern generating section, in accordance with the timing signals output from the timing generating section.

Abstract: A method replaces a delay amount measurement in which an initially set value of a counter is determined by a technique which replaces measurement of a delay amount, whereby a time required for calibration of a delay circuit can be reduced. One counter set value of a plurality of counter set values is loaded, a delay lock loop circuit is switched to a lock mode, and a sequence circuit of a cycle slip detection circuit is reset. Thereafter, a cycle slip detection signal output from the sequence circuit is read, and on the basis of this cycle slip detection signal, it is judged whether or not an output signal of a delay circuit causes cycle slip. If the cycle slip is caused, the counter set value is switched. On the other hand, if any cycle slip is not caused, the counter set value is locked, thereby terminating the process.

Abstract: A timing generator reduces operation-dependent power consumption (AC component) and noises generated from a clock distribution circuit itself in distributing a clock, and further reduces a skew attributed to the clock distribution. A clock distribution circuit 20 for distributing the clock to timing generating sections 10-l to 10-n has a clock main path 21 connected to a main path buffer 24 and a clock return path 26 connected to a return path buffer 27. A load capacity of the main path buffer 24 is equal to that of the return path buffer 27. Biases of the buffers are the same potential and are generated by a delay locked-loop circuit 30. A propagation delay time of the clock distribution circuit is controlled so as to be an integral multiple of a clock period.