Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A highly reliable and high speed ferroelectric memory having a high degree of integration. In a ferroelectric memory having a multiple of memory cells M1, each constituted by one transistor and one ferroelectric capacitor, in the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage on a storage node ST1 stores information in a DRAM mode. Both the electric potential at the plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are Vcc/2. When the a power supply voltage is turned on, a polarization state is detected as a ferroelectric memory of a plate electric potential of Vcc/2 and a precharge electric potential of Vss (or Vcc) and the read operation is performed a FERAM mode.

Abstract: A semiconductor memory is provided which includes a voltage converter supplying an internal supply voltage in proportion to the greater one of two reference voltages to a circuit in the semiconductor memory. The voltage converter includes a circuit which is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as a voltage dividing circuit. The memory also includes a word line booster for boosting the internal supply voltage.

Abstract: An apparatus includes a constant voltage generator for generating a voltage based on a difference between threshold voltages of two MOS transistors, and a voltage sampling device for sampling the output voltage of the constant voltage generator circuit, wherein the voltage sampling device samples the output voltage of the constant voltage generator before an electric source switch for the constant voltage generator is turned off.

Abstract: A highly reliable and high speed ferroelectric memory having high degree of integration is provided. In a ferroelectric memory having a plurality of memory cells M1 each constituted by one transistor and one ferroelectric capacitor. In the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage of a storage node ST1 is utilized as the stored information. Both an electric potential at a plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are made Vcc/2.

Abstract: An air-cooled oil-free rotary-type compressor in accordance with the invention includes a first air cooler including a plurality of cooling pipes, a check valve, and a second air cooler. The first air cooler, the check valve and the second air cooler are provided in a passage of compressed air discharged from a compressor body. The second air cooler is disposed in a first cooling air flow direction and the second air cooler is disposed in a second cooling air flow direction substantially perpendicular to the first cooling air flow direction. The plurality of cooling pipes of the first air cooler are arranged along the second cooling air flow direction.

Abstract: A voltage conversion circuit of the present invention is equipped with means for generating a first voltage stabilized with respect to ground potential of a semiconductor integrated circuit device including the circuit, means for generating second voltage stabilized with respect to an external supply voltage of the semiconductor integrated circuit device, and selection means for selecting either the first voltage or the second voltage. The first voltage age, stabilized with respect to the ground potential, is selected and used as the voltage at the time of normal operation, and the second voltage, stabilized with respect to the external supply voltage, is selected and used at the time of aging test. In this case, means for trimming the first voltage and/or the second voltage is, preferably, provided to raise the voltage accuracy.

Abstract: In a voltage converter provided in a semiconductor memory and supplying an internal supply voltage to a circuit in the semiconductor memory, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as voltage dividing means. The memory also includes a word line booster for boosting the internal supply voltage.

Abstract: In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.

Abstract: The semiconductor device has more-significant global data lines and less-significant data lines hierarchically formed, and switches for controlling the more-significant global data lines and the less-significant data lines to be connected each other. In addition, the semiconductor device has the unit for precharging the global data lines independently of the data lines.

Abstract: An apparatus includes a constant voltage generator for generating a voltage based on a difference between threshold voltages of two MOS transistors, and a voltage sampling device for sampling the output voltage of the constant voltage generator circuit, wherein the voltage sampling device samples the output voltage of the constant voltage generator before an electric source switch for the constant voltage generator is turned off.

Abstract: A voltage limiter circuit is disposed in a semiconductor IC chip in order to reduce an operating voltage of an internal circuit of a scaled-down element. A small capacitance of a Vcc wiring by the disposition constitutes a resonance circuit together with an inductance of the Vcc wiring. Resonance at the resonance circuit causes large variation of a supply current and noise. An additional capacitance is connected between the Vcc wiring and a Vss wiring in order to suppress the variation and noise. The capacitance is formed by a PN junction and is connected in series to a damping resistance.

Abstract: Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

Abstract: A method of producing an oil-free screw compressor has the following steps: preparing a semi-finished metallic female rotor which has a spiral profile, and a semi-finished metallic male rotor which has a spiral profile; forming a metallic coating film containing particles of grinding material on the surface of the semi-finished female rotor; forming, on the surface of the semi-finished male rotor, a coating film of a material softer than the metallic coating film on the female rotor; grinding the surfaces of the semi-finished rotors into predetermined configurations; mounting the ground rotors on bearings so that the rotors are assembled in a rotor casing with a substantially constant spacing held between the axes of the semi-finished rotors; mounting timing gears on the rotors so as to drivingly connect the rotors each other; and driving the rotors by driving means while restraining the back lash in the rotating direction by means of the timing gears and applying a compression load to the rotors so that the

Abstract: An oil-free scroll compressor comprising a plurality of oil-free scroll compressing mechanism blocks, each for compressing a gas, and a motor or motors for driving the plurality of oil-free scroll compressing mechanism blocks. In operation, an air is suctioned into the compressor through a filter and a throttle valve and then divided and sucked into first and second oil-free scroll compressing mechanism blocks, which act to increase the pressure of the air to a predetermined pressure. The compressed air is cooled by an after-cooler and supplied to the compressed air user side. The scroll compressing mechanism blocks are driven by a dual-shaft motor through belts. Under no-load condition, the throttle valve is closed and a release valve is opened, whereby the compressed air held between the blocks and check valves is released.

Abstract: A semiconductor storage device is provided which minimizes current consumption by using a circuit which is fed by charges stored in a parasitic capacitance of another circuit. To this end, short-circuiting switches SP and SN are provided respectively between first common source lines PP1 and PN1 and second common source lines PP2 and PN2 of the semiconductor device. Electric charges on the first common source lines which have been amplified to its normal amplitude change the voltage level of the second common source lines. A data line connected to the second common source line is amplified to half of the normal amplitude. Thereafter, the signal on the data line is amplified by a sense amplifier. As a result, the charge and discharge currents on the data line are substantially halved compared to the conventional device.

Abstract: A device parameter of a switching transistor is set in such a way that a leakage current of the switching transistor making up a power source switch which is turned off in a stand-by state is smaller than the sum total of subthreshold currents of P-channel or N-channel MOS transistors in an off state of a plurality of CMOS circuits. Therefore, the currents which flow through the plurality of CMOS circuits in the stand-by state are not determined by the subthreshold current but are determined by a small leakage current of the switching transistor. As a result, even when the CMOS circuit is shrunken and the subthreshold current increases, it is possible to reduce the current consumption in the stand-by state.

Abstract: In a voltage converter provided in a semiconductor device and supplying an internal supply voltage to a circuit in the semiconductor device, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. Another circuit selects the first voltage when the semiconductor device is in a state of a standard operation and selects the second voltage when the device is in another state of operation, such as testing or aging. The selected voltage may be converted by a differential amplifier which is constituted by a load of P-channel MOS transistors and a source-coupled pair of N-channel MOS transistors. An output of the differential amplifier is fed back through a directly coupled voltage lowering circuit which generates the converted output.