Abstract: In a door mirror device for a vehicle, an retracting device supports a mirror by coupling a mirror angle adjusting device for holding the mirror with a holding portion of a frame and coupling the retracting device fixed to a vehicle body with a supporting portion of the frame. The frame is provided with the holding portion and the supporting portion formed by drawing a frame-forming metal plate which has been formed by pressing, and a portion connecting the holding portion and the supporting portion is provided with a difference in level. Thus, the frame can have sufficient rigidity.

Abstract: A semiconductor memory such as a dynamic random access memory (DRAM), having a memory array which is divided into memory mats and a storage capacity of 16 M bits or more, features a defect recovery scheme through employing a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes a comparing circuit having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. In accordance with this, each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit.

Abstract: In a semiconductor integrated circuit device having a first circuit block operating on a power supply voltage supplied through an external terminal and a second circuit block operating on an internal voltage generated by a power supply circuit, a voltage having an absolute value greater than that of the internal voltage is generated by a charge pump circuit; variable impedance means is provided between the output voltage and the internal voltage; and a reference voltage and the internal voltage are compared by a differential amplifier circuit operating on the output voltage generated by the charge pump circuit and the variable impedance means is controlled such that those voltages agree with each other.

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Abstract: A tandem type color image forming apparatus has a plurality of image forming units. These units includes at least a plurality of spaced photosensitive drums, and a plurality of developing rollers for developing with toners electrostatic latent images formed on these photosensitive drums. The image forming units except the image forming unit for black color that may be highly frequently used are accommodated in the same first housing. The unit for black color is accommodated in another second housing. The first and second housings are made to be attachable to and detachable from the chassis of the apparatus main body independently of each other. Only an image forming unit with high frequency of inspection or maintenance can separately be detached, so that the work load for inspection or maintenance is reduced, and handling of the apparatus is easy.

Abstract: A housing for a member disposed at a vehicle exterior is formed by assembling a plurality of parts substantially in a vehicle longitudinal direction. At a matching portion when the plurality of parts are assembled together substantially in the vehicle longitudinal direction, a housing outer side end portion of a matching surface substantially at a vehicle frontward side is displaced further outward than a housing outer side end portion of a matching surface substantially at a vehicle rearward side. Or, the housing outer side end portion of the matching surface substantially at the vehicle rearward side may have a curved surface or a flat surface.

Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

Abstract: A field-effect semiconductor element implemented with a reduced number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature. In accordance with one embodiment, a carrier confinement region, isolated from a channel and a gate of the semiconductor FET element, is provided to operate as a storage node for trapping the carrier or carriers.

Abstract: A compressed air production facility includes at least one variable speed compressor and a plurality of constant speed compressor, which are connected in parallel with one another. The variable speed compressor and the plurality of constant speed compressors are capacitively controlled with the use of a pressure in an air reservoir into which discharge air from these compressor are led. Both upper limit pressure at which the variable speed compressor is turned into its load operation mode into its unload operation mode and a lower limit pressure at which the variable speed compressor is turned into its unload operation mode into its load operation mode are set between an upper limit change-over pressure at which all of the plurality of constant speed compressors are turned into their load operation into their unload operation and a lower limit change-over pressure at which all of the plurality of constant speed compressors are changed over from their unload operation into their load operation.

Abstract: To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, address for salvaging defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit, thereby, a special process is not needed in forming the nonvolatile memory element, that is, the nonvolatile memory element can be formed in a process of forming CMOS device and apparatus of laser beam for programming is not needed since the programming is carried out in testing, time necessary for programming can be shortened and therefore, testing cost can be reduced.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. Input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.

Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

Abstract: A screw rotor for use in screw compressors and screw vacuum pumps comprises a pair of rotors including a male rotor and a female rotor. These rotors have helical lobes in an axial direction and mesh with each other to form a compression chamber. Depending upon a lobe configuration of the rotors, suction pressure and discharge pressure, a negative torque for self-rotation as well as a positive torque opposing to rotation due to a compression action is generated on the female rotor in operation. This phenomenon generates when a value obtained by integrating a torque acting on the female rotor over an entire cross section in an axial direction of the rotors becomes negative. When the negative torque is generated, noises due to tooth separating vibration is caused. Then, a lobe profile is defined such that a magnitude of the negative torque is smaller than that of the positive torque in respective cross sections of the female rotor.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

Abstract: A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. In the lattice-like delay circuit, input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of a plurality of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.

Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A semiconductor memory device is provided which includes a memory cell array, a read circuit which reads data from said memory cell array, and an external terminal which receives an external clock signal. A first input circuit receives the external clock signal and outputs a first internal clock signal delayed from the external clock signal. A second input circuit receives the first internal clock signal and outputs a second internal clock signal delayed from the first internal clock signal. The memory device also includes a circuit which counts a clock signal having a frequency higher than that of the external clock signal and a circuit which starts the counting in response to the second internal clock signal, reverses the direction of said counting in response to the first internal clock signal and detects when a count of said counting circuit again reaches the count at the start of said counting, thereby outputting a timing signal therefrom.