Abstract: An antifuse memory cell having a P.sup.+ polysilicon doping in a region directly under an intrinsic silicon programming layer. The P.sup.+ polysilicon region is surrounded by an N.sup.- polysilicon doped region, and the two regions are sandwiched between layers of silicon dioxide insulation. The interface between the two regions is a P-N junction, in fact, a diode. The diode does not suffer from a diffusion current that increases with increasing levels of N.sup.- doping, therefore the N.sup.- polysilicon can be heavily doped to yield a very conductive bit line interconnect for a memory matrix. The interconnect line widths can be very narrow, and further microminiaturization is aided thereby. The top metalization is aluminum and serves as a word line interconnect in the memory matrix.

Abstract: A static random access memory integrated circuit comprises a plurality of memory cells that contain load resistance elements formed as load resistance strips in proximity of active and passive components of the integrated circuit. A conductive layer formed between the load resistance strips and such components functions as a shield to protect the load resistance strips of a memory cell from the effects of electric fields established from operation of such components, such as, MOS transistors underlying the load resistance strips between which the shield is formed. With the load resistance strips protected by the presence of the shield, their resistance values will not vary or be effected by imposing electric fields from the operation of the MOS transistors.

Abstract: A wiring or conductor structure for an integrated circuit structure of a semiconductor device is designed to provide for extended values in integrated passive components, for example, resistance values in a memory cell of a high resistance load type static RAM. Extended values of high resistance polycrystalline silicon resistances formed in conductor films are achieved by effectively increasing the length of the films and, therefore, the regions of resistance without changing or increasing the size or scale of the semiconductor device. This is accomplished by employing double wiring or conductor layers which are electrically connected permitting a lateral extension of the integrated and patterned resistance region in at least one of the wiring layers while retaining or further reducing the integration scale of the active and passive components comprising the integrated circuit structure.

Abstract: A standing-wave accelerator including a plurality of accelerating cavities arranged along the axis direction of the accelerator; a plurality of coupling cavities provided between the two-adjacent accelerating cavities; at least one of the coupling cavities is provided with a detuning device for detuning the coupling cavity; and the detuning device is provided to be inserted from a first wall of the coupling cavity to extend until it comes into contact with a second wall thereof, spacedly passed between a pair of inwardly projecting posts.