Patents by Inventor Masaki Arai

Masaki Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210081239
    Abstract: An information processing apparatus, a non-transitory computer-readable storage medium for storing an information processing program, and an information processing method are described. In an embodiment, provided is a solution to efficiently determine a degree to which each of a plurality of simplification processes is applied to a program. For example, an information processing apparatus includes: a storage device that stores program instructions; and a processor that executes the program instructions including selecting a first candidate value from among a plurality of candidate values included in a first set, based on an evaluation result for a plurality of execution results generated at a first position, and selecting a second candidate value from among the plurality of candidate values included in a second set, based on an evaluation result for the plurality of execution results generated at a second position.
    Type: Application
    Filed: July 29, 2020
    Publication date: March 18, 2021
    Applicant: FUJITSU LIMITED
    Inventor: MASAKI ARAI
  • Publication number: 20210073049
    Abstract: A barrier synchronization system, a parallel information processing apparatus, and the like are described in the embodiments. In an example, provided is a solution to reduce latency time and improve processing speed in barrier synchronization.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 11, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Kanae Nakagawa, MASAKI ARAI, YASUMOTO TOMITA
  • Publication number: 20210073048
    Abstract: A barrier synchronization circuit that performs barrier synchronization of a plurality of processes executed in parallel by a plurality of processing circuits, the barrier synchronization circuit includes a first determination circuit configured to determine whether the number of first processing circuits among the plurality of the processing circuits is equal to or greater than a first threshold value, the first processing circuits having completed the process, and an instruction circuit configured to instruct a second processing circuit among the plurality of the processing circuits to forcibly stop the process when it is determined that the number is equal to or greater than the first threshold value by the first determination circuit, the second processing circuit having not completed the process.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 11, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Kanae Nakagawa, MASAKI ARAI, YASUMOTO TOMITA
  • Publication number: 20210037070
    Abstract: An information processing system includes a plurality of communication terminals, and an information processing apparatus. The information processing apparatus includes first circuitry to acquire one or more images of a shared screen; store the acquired one or more images as one or more captured image; receive a selection of a particular captured image that is not to be displayed on at least one communication terminal of the plurality of communication terminals; generate data of a screen including the one or more captured images to be displayed on the at least one communication terminal, the screen not displaying at least a part of the one or more captured images based on the received selection; and transmit the generated data to the at least one communication terminal. Each of the plurality of communication terminals includes second circuitry configured to display the screen based on the received data.
    Type: Application
    Filed: July 28, 2020
    Publication date: February 4, 2021
    Applicant: Ricoh Company, Ltd.
    Inventor: MASAKI ARAI
  • Publication number: 20210019128
    Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: receive input of an input program in which a plurality of statements is written in a loop; generate a counting program for causing a computing machinery to execute a process of counting the number of cache misses and the number of cache hits that are expected when the loop is executed for each of pairs of the statements by rewriting the input program; and split the loop into a plurality of loops based on the number of cache misses and the number of cache hits counted in the process.
    Type: Application
    Filed: June 16, 2020
    Publication date: January 21, 2021
    Applicant: FUJITSU LIMITED
    Inventor: MASAKI ARAI
  • Publication number: 20210004196
    Abstract: According to one or more embodiments, an information processing system includes a plurality of communication terminals, each installed with a web browser; and an information processing apparatus. The information processing apparatus includes first circuitry configured to: determine occurrence of a trigger to capture an image of a shared screen to be shared by the plurality of communication terminals; generate data of a web page including the image of the shared screen captured based on the occurrence of the trigger; and transmit the data of the web page to the plurality of communication terminals. Each of the plurality of communication terminals includes second circuitry configured to display the web page including the image of the shared screen based on the data received from the information processing apparatus.
    Type: Application
    Filed: June 26, 2020
    Publication date: January 7, 2021
    Applicant: Ricoh Company, Ltd.
    Inventors: MASAKI ARAI, HIROKAZU IIDA
  • Patent number: 10715687
    Abstract: An information processing system includes one or more information processing apparatuses each of which performs a plurality of programs to implement functions.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: July 14, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Yuuichiroh Hayashi, Kai Kodama, Masaki Arai
  • Patent number: 10713167
    Abstract: An information processing apparatus includes a first memory and a processor coupled to the first memory. The processor is configured to acquire a first address in the first memory, at which an instruction included in a target program is stored. The processor is configured to simulate access to a second memory, such as a cache memory, corresponding to an access request for access to the first address on a basis of configuration information of the second memory. The processor is configured to generate first information, such as cache profile information, indicating whether the access to the second memory regarding the instruction is a hit or miss. The processor may be configured to acquire a number of cache misses for each of a plurality of pieces of arrangement information, and select a piece of arrangement information where the number of cache misses is smallest.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 14, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Masaki Arai
  • Patent number: 10366015
    Abstract: A method for a cache miss estimation includes; generating a variable range of a possible value of loop variables relevant to a specific array; generating first expression of number of times indicating the number of times the specific position of a specific loop is executed; generating second expression of number of times indicating the number of times the data of the access target is stored in the cache; generating third expression of number of times indicating the number of times the data of the access target is removed from the cache; generating fourth expression of number of times, from a generated conflict miss cause common expression, indicating the number of times the data of the access target is stored in the cache; and estimating a number of cache miss based on the difference between the first and the second expressions and the difference between the third and the forth expressions.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: July 30, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Masaki Arai
  • Patent number: 10277546
    Abstract: An information processing system is implemented by an information processing apparatus and terminals connected to the information processing apparatus. The information processing system includes a destination determiner that determines a destination terminal of the terminals based on the right of a sender terminal of the terminals that has sent a message, a message generator that generates a message adapted for the destination terminal based on the message sent from the sender terminal, a transmitter that sends the message generated by the message generator to the destination terminal, and a display unit that is provided in each of the terminals and displays the message sent from the transmitter in a display format corresponding to the right of the each of the terminals.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: April 30, 2019
    Assignee: Ricoh Company, Ltd.
    Inventor: Masaki Arai
  • Publication number: 20190042426
    Abstract: An information processing apparatus includes a first memory and a processor coupled to the first memory. The processor is configured to acquire a first address in the first memory, at which data indicating an instruction included in a target program is stored. The processor is configured to simulate access to a second memory corresponding to an access request for access to the first address on a basis of configuration information of the second memory. The processor is configured to generate first information that indicates whether the access to the second memory is successful regarding the instruction.
    Type: Application
    Filed: July 30, 2018
    Publication date: February 7, 2019
    Applicant: FUJITSU LIMITED
    Inventor: MASAKI ARAI
  • Publication number: 20180343352
    Abstract: An information processing system includes one or more information processing apparatuses each of which performs a plurality of programs to implement functions.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 29, 2018
    Inventors: Yuuichiroh HAYASHI, Kai Kodama, Masaki Arai
  • Patent number: 10082676
    Abstract: A first correction signal creation unit splits an angular velocity signal of an ultra low-low frequency band from an angular velocity signal of an X-axis angular velocity sensor and outputs a first correction signal amplified based on signal output characteristics of the angular velocity sensor. A second correction signal creation unit splits an angular velocity signal of a low-high frequency band from the angular velocity signal and outputs a second correction signal amplified based on the signal output characteristics of the angular velocity sensor. An addition computation unit creates a composite correction signal in which the first correction signal and the second correction signal are composed, and a drive computation unit creates a drive signal based on the composite correction signal. A driver drives the X-axis actuator based on the drive signal, displaces the correction optical element, and corrects shake of an image.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: September 25, 2018
    Assignee: FUJIFILM Corporation
    Inventors: Shigeyuki Takano, Masaki Arai, Naoki Yamaguchi, Hiromitsu Kaburagi
  • Patent number: 9909784
    Abstract: An outdoor unit of an air conditioner coupled to an indoor unit by a liquid pipe and a gas pipe, includes: a compressor; an outdoor heat exchanger; a discharge pipe coupled to a refrigerant discharge side of the compressor; an intake pipe coupled to a refrigerant intake side of the compressor; an outdoor-unit high-pressure gas pipe coupled to the discharge pipe; an outdoor-unit low-pressure gas pipe coupled to the intake pipe; an outdoor-unit liquid pipe that couples a first refrigerant entry/exit opening of the outdoor heat exchanger and the liquid pipe together; a bypass pipe coupled to the outdoor-unit liquid pipe; a first flow-passage switcher coupled to a second refrigerant entry/exit opening of the outdoor heat exchanger, the discharge pipe, the intake pipe, and the bypass pipe; and a second flow-passage switcher coupled to the gas pipe, the outdoor-unit high-pressure gas pipe, and the outdoor-unit low-pressure gas pipe.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: March 6, 2018
    Assignee: FUJITSU GENERAL LIMITED
    Inventors: Kotaro Toya, Makoto Shimotani, Hideya Tamura, Takahiro Matsunaga, Shinju Watanabe, Koji Ogata, Masaki Arai, Yasuhiro Oka, Ken Nakashima, Toshihiro Takahashi, Masakazu Sato
  • Publication number: 20170357601
    Abstract: A method for a cache miss estimation includes; generating a variable range of a possible value of loop variables relevant to a specific array; generating first expression of number of times indicating the number of times the specific position of a specific loop is executed; generating second expression of number of times indicating the number of times the data of the access target is stored in the cache; generating third expression of number of times indicating the number of times the data of the access target is removed from the cache; generating fourth expression of number of times, from a generated conflict miss cause common expression, indicating the number of times the data of the access target is stored in the cache; and estimating a number of cache miss based on the difference between the first and the second expressions and the difference between the third and the forth expressions.
    Type: Application
    Filed: April 27, 2017
    Publication date: December 14, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Masaki ARAI
  • Patent number: 9699633
    Abstract: An input/output system interconnects a mobile terminal, a cooperative processing apparatus, and a plurality of electronic devices, and is configured to implement a cooperative process of prompting an electronic device corresponding to an input apparatus to input electronic data and prompting an electronic device corresponding to an output apparatus to output the input electronic data.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: July 4, 2017
    Assignee: Ricoh Company, Ltd.
    Inventor: Masaki Arai
  • Patent number: 9563639
    Abstract: An information storing device includes a storage device in which one or more storage areas are generated for storing electronic data therein, wherein in the storage device at least one of first and second processes is set on a storage area basis; a storing part configured to, when the information storing device has received electronic data and a designation of the storage area from one of a plurality of electronic apparatuses, store the received electronic data in the storage area designated by the received designation; and an executing part configured to, when the received electronic data is stored by the storing part, perform the first process on the stored electronic data if the first process is set in the storage area in which said electronic data is stored, and perform the second process using the stored electronic data if the second process is set in the storage area in which said electronic data is stored.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: February 7, 2017
    Assignee: Ricoh Company, Ltd.
    Inventor: Masaki Arai
  • Publication number: 20160364220
    Abstract: Based on a description of loop processing in a source code, for each of count values each indicating a number of times the loop processing has been iterated, instructions of one loop portion corresponding to the each count value and a dependence relationship between a pair of instructions having a data dependence are displayed. Upon receiving an input to specify that an instruction group including instructions having no dependences on each other is executed by an identical processor, usage efficiency of a cache memory, an alignment degree of used data, and a number of threads at a time of parallel execution are calculated and displayed. Upon receiving an input to determine the instruction group, the source code is compiled, and loop optimization using a polyhedral model under constraints in which the instruction group is executed by the identical processor is performed on the loop processing.
    Type: Application
    Filed: May 11, 2016
    Publication date: December 15, 2016
    Applicant: FUJITSU LIMITED
    Inventor: Masaki ARAI
  • Publication number: 20160360390
    Abstract: An input/output system interconnects a mobile terminal, a cooperative processing apparatus, and a plurality of electronic devices, and is configured to implement a cooperative process of prompting an electronic device corresponding to an input apparatus to input electronic data and prompting an electronic device corresponding to an output apparatus to output the input electronic data.
    Type: Application
    Filed: August 17, 2016
    Publication date: December 8, 2016
    Applicant: Ricoh Company, Ltd.
    Inventor: Masaki ARAI
  • Patent number: 9451432
    Abstract: An input/output system interconnects a mobile terminal, a cooperative processing apparatus, and a plurality of electronic devices, and is configured to implement a cooperative process of prompting an electronic device corresponding to an input apparatus to input electronic data and prompting an electronic device corresponding to an output apparatus to output the input electronic data.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: September 20, 2016
    Assignee: Ricoh Company, Ltd.
    Inventor: Masaki Arai