Abstract: An isolation amplifier of an embodiment includes: a primary circuit including an encoder configured to encode an input signal and output the encoded input signal and an anomaly detection circuit configured to detect anomaly having occurred to the input signal and generate a detection signal; an isolation unit configured to insulate the primary circuit from a secondary circuit; an output circuit configured to generate an output signal corresponding to the input signal; and an anomaly-input sensing-output circuit configured to generate an output signal from the secondary circuit by changing the output signal from the output circuit based on the detection signal.

Abstract: A knee airbag device including an airbag cushion, a storage case in which is formed a horizontally long opening part where the expanded and deployed airbag cushion pops outs, a first flap for covering the airbag cushion exposed through the opening part such that the airbag cushion is retained in the storage case, and having a first weak part that breaks when pressed by the airbag cushion during expansion and deployment and a second flap, which is a component with a larger dimension in a length direction than the first flap and for covering an outer surface of the first flap so as to transverse in a short direction of the opening part a center part of the airbag cushion in a lateral direction, the second flap having a second weak part that breaks when pressed by the airbag cushion after rupture of the first weak part.

Abstract: A non-transitory computer-readable recording medium stores an information processing program for causing a computer to execute processing including: classifying a plurality of calculation nodes each in charge of arithmetic processing regarding to an access destination according to an identifier of an own node by using a cache into a plurality of groups, based on a remainder obtained by dividing a value that corresponds to the access destination by the number of sets in the cache; and acquiring profile information of the cache, that corresponds to any one group, by performing a simulation that imitates an access to the cache in the arithmetic processing, for at least any one of the calculation nodes classified into any one group, for any one of the plurality of groups.

Abstract: A barrier synchronization circuit that performs barrier synchronization of a plurality of processes executed in parallel by a plurality of processing circuits, the barrier synchronization circuit includes a first determination circuit configured to determine whether the number of first processing circuits among the plurality of the processing circuits is equal to or greater than a first threshold value, the first processing circuits having completed the process, and an instruction circuit configured to instruct a second processing circuit among the plurality of the processing circuits to forcibly stop the process when it is determined that the number is equal to or greater than the first threshold value by the first determination circuit, the second processing circuit having not completed the process.

Abstract: A non-transitory computer-readable recording medium storing an arithmetic processing program that causes a computer to execute a process, the process includes, in a case of obtaining a result of product (r=A×v) of a matrix A expressed in a sparse matrix format and a vector v, grouping rows with a column of non-zero data within a range that does not exceed a slot size of a scratchpad memory, allocating a slot to each column of the non-zero data in the grouped rows, and transferring, at a time of processing the rows for each group, data of the vector v that corresponds to each column to the slot allocated to each column in processing of a first row of the group.

Abstract: A recording medium stores a program for generating a source code that indicates processing on a sparse matrix and for causing a computer to execute a process including: acquiring second codes by optimizing, with a convex polyhedral model, a first code in which loop processing on a matrix is written in a static control part format; converting the second codes into source code candidates, based on sparse matrix information that indicates a variable that represents a non-zero element of the sparse matrix, expression information that indicates an operation expression that corresponds to a function included in the second codes, and data type information that indicates a type to be used for the variable; and selecting the source code from among the source code candidates in accordance with evaluation of processing performance for the sparse matrix in a case where each of the source code candidates is used.

Abstract: Provided is an anti-vibration device which includes a shake correction unit, the anti-vibration device including a first vibration detector that is disposed in the shake correction unit, a second vibration detector that is disposed outside the shake correction unit, and a processor. The processor performs anti-vibration control based on a first output value output from the first vibration detector and a second output value output from the second vibration detector.

Abstract: A program rewrite method executed by a computer, the method includes rewriting a program to output a first output group by performing operations for a first variable among a plurality of variables with a plurality of data types; rewriting the program to output a second output group by performing operations for a second variable among the plurality of variables with a plurality of data types; identifying, from the first output group and the second output group, a third output group that satisfied a predetermined criterion as a result of executing the rewritten programs; determining a data type that corresponds to the third output group as a use data type; and outputting a program in which the use data type is set for each of the plurality of variables.

Abstract: A barrier synchronization system, a parallel information processing apparatus, and the like are described in the embodiments. In an example, provided is a solution to reduce latency time and improve processing speed in barrier synchronization.

Abstract: An information processing apparatus, a non-transitory computer-readable storage medium for storing an information processing program, and an information processing method are described. In an embodiment, provided is a solution to efficiently determine a degree to which each of a plurality of simplification processes is applied to a program. For example, an information processing apparatus includes: a storage device that stores program instructions; and a processor that executes the program instructions including selecting a first candidate value from among a plurality of candidate values included in a first set, based on an evaluation result for a plurality of execution results generated at a first position, and selecting a second candidate value from among the plurality of candidate values included in a second set, based on an evaluation result for the plurality of execution results generated at a second position.

Abstract: An optical device which includes an optical system includes a sensor that detects vibration on the optical device, an anti-vibration mechanism that includes a drive source driven based on a result of detection performed by the sensor, a fixation mechanism that fixes a position of the anti-vibration mechanism by coming into contact with a specific portion of the anti-vibration mechanism, and a processor that performs control with respect to the drive source such that interference between the specific portion and the fixation mechanism does not occur while the fixation mechanism is switching from one of a fixation state, in which the fixation mechanism fixes the position of the anti-vibration mechanism, and a release state, in which the fixation state of the fixation mechanism is released, to the other of the fixation state and the release state.

Abstract: A non-transitory computer-readable recording medium stores an information acquisition program for causing a computer to execute a process, the process including receiving sparse matrix data that indicates a position of a non-zero element in a sparse matrix that is referred in sparse matrix processing included in a target program, and acquiring, using the sparse matrix data, cache access information that indicates an access status to a cache memory occurred in the sparse matrix processing.

Abstract: According to one or more embodiments, an information processing system includes a plurality of communication terminals, each installed with a web browser; and an information processing apparatus. The information processing apparatus includes first circuitry configured to: determine occurrence of a trigger to capture an image of a shared screen to be shared by the plurality of communication terminals; generate data of a web page including the image of the shared screen captured based on the occurrence of the trigger; and transmit the data of the web page to the plurality of communication terminals. Each of the plurality of communication terminals includes second circuitry configured to display the web page including the image of the shared screen based on the data received from the information processing apparatus.

Abstract: An information processing apparatus is connected to a first communication terminal and a second communication terminal through a network. The information processing apparatus includes circuitry. The circuitry receives operation information indicating an operation performed on a capture image at the second communication terminal, the capture image being an image captured by the second communication terminal from a shared screen shared by the first communication terminal, the second communication terminal, and another communication terminal. The circuitry identifies a part where the operation is performed on the capture image, based on the received operation information. The circuitry transmits information on the part where the operation is performed to the first communication terminal.

Abstract: A program rewrite method executed by a computer, the method includes rewriting a program to output a first output group by performing operations for a first variable among a plurality of variables with a plurality of data types; rewriting the program to output a second output group by performing operations for a second variable among the plurality of variables with a plurality of data types; identifying, from the first output group and the second output group, a third output group that satisfied a predetermined criterion as a result of executing the rewritten programs; determining a data type that corresponds to the third output group as a use data type; and outputting a program in which the use data type is set for each of the plurality of variables.

Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: receive input of an input program in which a plurality of statements is written in a loop; generate a counting program for causing a computing machinery to execute a process of counting the number of cache misses and the number of cache hits that are expected when the loop is executed for each of pairs of the statements by rewriting the input program; and split the loop into a plurality of loops based on the number of cache misses and the number of cache hits counted in the process.

Abstract: An information processing apparatus, a non-transitory computer-readable storage medium for storing an information processing program, and an information processing method are described. In an embodiment, provided is a solution to efficiently determine a degree to which each of a plurality of simplification processes is applied to a program. For example, an information processing apparatus includes: a storage device that stores program instructions; and a processor that executes the program instructions including selecting a first candidate value from among a plurality of candidate values included in a first set, based on an evaluation result for a plurality of execution results generated at a first position, and selecting a second candidate value from among the plurality of candidate values included in a second set, based on an evaluation result for the plurality of execution results generated at a second position.

Abstract: A barrier synchronization circuit that performs barrier synchronization of a plurality of processes executed in parallel by a plurality of processing circuits, the barrier synchronization circuit includes a first determination circuit configured to determine whether the number of first processing circuits among the plurality of the processing circuits is equal to or greater than a first threshold value, the first processing circuits having completed the process, and an instruction circuit configured to instruct a second processing circuit among the plurality of the processing circuits to forcibly stop the process when it is determined that the number is equal to or greater than the first threshold value by the first determination circuit, the second processing circuit having not completed the process.

Abstract: A barrier synchronization system, a parallel information processing apparatus, and the like are described in the embodiments. In an example, provided is a solution to reduce latency time and improve processing speed in barrier synchronization.

Abstract: An information processing system includes a plurality of communication terminals, and an information processing apparatus. The information processing apparatus includes first circuitry to acquire one or more images of a shared screen; store the acquired one or more images as one or more captured image; receive a selection of a particular captured image that is not to be displayed on at least one communication terminal of the plurality of communication terminals; generate data of a screen including the one or more captured images to be displayed on the at least one communication terminal, the screen not displaying at least a part of the one or more captured images based on the received selection; and transmit the generated data to the at least one communication terminal. Each of the plurality of communication terminals includes second circuitry configured to display the screen based on the received data.