Abstract: A memory system according to an embodiment includes: a first chip including a first plane and a first input/output circuit; and a controller which is capable of issuing a command for controlling the first chip. The first plane includes: a first memory cell array having a plurality of first memory cell transistors; and a first latch circuit which is capable of storing first read data read from the first memory cell array. The first input/output circuit includes a first FIFO circuit which is capable of fetching the first read data from the first latch circuit. The controller is capable of transmitting to the first chip a first command for ordering fetching of the first read data from the first latch circuit to the first FIFO circuit during a period in which a read operation is executed on the first plane.

Abstract: A semiconductor storage device includes a memory string, a sense amplifier connected to the memory string, first, second, third, and fourth latch circuits that are each connected to the sense amplifier, a first wiring connected to the sense amplifier, the first latch circuit and the second latch circuit, a second wiring connected to the third latch circuit, a third wiring connected to the fourth latch circuit, a first switch transistor between the first wiring and the third wiring, a second switch transistor between the first wiring and the second wiring, and a third switch transistor between the second wiring and the third wiring.

Abstract: A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines.

Abstract: A semiconductor memory device includes a first plane including a memory cell array, a second plane including a memory cell array, a control circuit configured to control operations performed on the first and second planes separately and independently, and first register for storing a condition value related to a condition of an operation to be performed on a plane. When a first command to store a first condition value in a first address of the first register is received, the control circuit specifies a plane to which the first address has been allocated. When the first plane is specified by the first address, the control circuit determines whether the first plane is in a command receivable state. Then, when the control circuit determines that the first plane is in the command receivable state, the control circuit stores the first condition value in the first address of the first register.

Abstract: A semiconductor memory device includes a first plane including a memory cell array, a second plane including a memory cell array, a control circuit configured to control operations performed on the first and second planes separately and independently, and first register for storing a condition value related to a condition of an operation to be performed on a plane. When a first command to store a first condition value in a first address of the first register is received, the control circuit specifies a plane to which the first address has been allocated. When the first plane is specified by the first address, the control circuit determines whether the first plane is in a command receivable state. Then, when the control circuit determines that the first plane is in the command receivable state, the control circuit stores the first condition value in the first address of the first register.

Abstract: A semiconductor memory device includes a plurality of memory strings each of which includes a series of memory cells that each store data having n bits (n?3), word lines, each connected in common to memory cells of different memory strings, and a control circuit which controls a first write operation and a second write operation. The first write operation includes a first step where a middle threshold voltage distribution is formed in memory cells and a second step following the first step where threshold voltages of some of the memory cells are increased, and the second write operation includes a step where threshold voltage distributions which correspond to the data having n bits is formed in the memory cells, wherein a write verify operation is performed after the first step but not after the second step of the first write operation.

Abstract: In one embodiment, a control circuit executes a first page writing operation, a first verify operations, a second page writing operation, a second verify operations, a step-up operation. The control circuit executes the first page writing operation which forms an intermediate distribution, and a first read operation which reads data form the intermediate distribution by using a determine voltage higher than a first verify voltage with a first value, and changes a second verify voltage based on the result of the first read operation.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, and a control circuit. A first memory cell stores first data of n bits, a second memory cell stores second data used to determine whether data of k bits is stored in the first memory cell, and the control circuit performs first determination of determining data read from the data of the second memory cell, performs second determination of determining data read from the second memory cell by supplying the first word line with a second read voltage different from the first read voltage, and outputs either one of a result obtained by reading the data stored in the first memory cell at the first read voltage and a result obtained by reading the data stored in the first memory cell at the second read voltage, based on a result of the second determination.

Abstract: A semiconductor memory device includes a plurality of memory strings each of which includes a series of memory cells that each store data having n bits (n?3), word lines, each connected in common to memory cells of different memory strings, and a control circuit which controls a first write operation and a second write operation. The first write operation includes a first step where a middle threshold voltage distribution is formed in memory cells and a second step following the first step where threshold voltages of some of the memory cells are increased, and the second write operation includes a step where threshold voltage distributions which correspond to the data having n bits is formed in the memory cells, wherein a write verify operation is performed after the first step but not after the second step of the first write operation.

Abstract: In one embodiment, a control circuit executes a first page writing operation, a first verify operations, a second page writing operation, a second verify operations, a step-up operation. The control circuit executes the first page writing operation which forms an intermediate distribution, and a first read operation which reads data form the intermediate distribution by using a determine voltage higher than a first verify voltage with a first value, and changes a second verify voltage based on the result of the first read operation.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, and a control circuit. A first memory cell stores first data of n bits, a second memory cell stores second data used to determine whether data of k bits is stored in the first memory cell, and the control circuit performs first determination of determining data read from the data of the second memory cell, performs second determination of determining data read from the second memory cell by supplying the first word line with a second read voltage different from the first read voltage, and outputs either one of a result obtained by reading the data stored in the first memory cell at the first read voltage and a result obtained by reading the data stored in the first memory cell at the second read voltage, based on a result of the second determination.

Abstract: A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.

Abstract: A nonvolatile semiconductor memory device and a nonvolatile memory system having a unit which suppresses erroneous reading of a nonvolatile semiconductor memory device of a multi-level memory system are provided. In the nonvolatile semiconductor memory device and the nonvolatile memory system of the multi-level memory system, a first verify voltage is used when data is written before a packaging process, and the verify voltage is switched to a second verify voltage lower than the first verify voltage when data is written after the packaging process.

Abstract: A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data memory circuit, a power generation circuit, and a controller. In the memory cell array, a plurality of memory cells which store two-or-more-bit data are arrayed in a matrix. When data is written to all memory cells connected to selected word lines, the controller performs a write operation with a write voltage obtained by adding the step-up voltage to the write voltage until a write count indicating a number of times by which writing is performed reaches a first write count. When the first write count is exceeded, the controller controls whether the step-up voltage is to be added or not, for each write operation.

Abstract: A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

Abstract: A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

Abstract: A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.