Abstract: A nonvolatile semiconductor memory device and a nonvolatile memory system having a unit which suppresses erroneous reading of a nonvolatile semiconductor memory device of a multi-level memory system are provided. In the nonvolatile semiconductor memory device and the nonvolatile memory system of the multi-level memory system, a first verify voltage is used when data is written before a packaging process, and the verify voltage is switched to a second verify voltage lower than the first verify voltage when data is written after the packaging process.

Abstract: A semiconductor integrated circuit device includes: a memory cell array composed of electrically rewritable memory cells; an internal voltage generating circuit having a boosting circuit for generating a voltage boosted from a supply voltage, and a voltage detecting circuit for detecting an output voltage of the boosting circuit as a monitor voltage and controlling on/off of the boosting circuit for holding the output voltage of the boosting circuit at a specified level, the internal voltage generating circuit outputting the output voltage of the boosting circuit as an internal voltage; a control circuit for controlling the internal voltage generating circuit; and a writing circuit for applying the internal voltage to the memory cell as a writing voltage when writing data into the memory cell, wherein the control circuit controls the internal voltage to a first voltage necessary for writing data into the memory cell when writing data into the memory cell, and to a second voltage lower than the first voltage i

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data memory circuit, a power generation circuit, and a controller. In the memory cell array, a plurality of memory cells which store two-or-more-bit data are arrayed in a matrix. When data is written to all memory cells connected to selected word lines, the controller performs a write operation with a write voltage obtained by adding the step-up voltage to the write voltage until a write count indicating a number of times by which writing is performed reaches a first write count. When the first write count is exceeded, the controller controls whether the step-up voltage is to be added or not, for each write operation.

Abstract: A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.

Abstract: A semiconductor integrated circuit device includes: a memory cell array composed of electrically rewritable memory cells; an internal voltage generating circuit having a boosting circuit for generating a voltage boosted from a supply voltage, and a voltage detecting circuit for detecting an output voltage of the boosting circuit as a monitor voltage and controlling on/off of the boosting circuit for holding the output voltage of the boosting circuit at a specified level, the internal voltage generating circuit outputting the output voltage of the boosting circuit as an internal voltage; a control circuit for controlling the internal voltage generating circuit; and a writing circuit for applying the internal voltage to the memory cell as a writing voltage when writing data into the memory cell, wherein the control circuit controls the internal voltage to a first voltage necessary for writing data into the memory cell when writing data into the memory cell, and to a second voltage lower than the first voltage i

Abstract: A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

Abstract: A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

Abstract: A semiconductor integrated circuit device includes: a memory cell array composed of electrically rewritable memory cells; an internal voltage generating circuit having a boosting circuit for generating a voltage boosted from a supply voltage, and a voltage detecting circuit for detecting an output voltage of the boosting circuit as a monitor voltage and controlling on/off of the boosting circuit for holding the output voltage of the boosting circuit at a specified level, the internal voltage generating circuit outputting the output voltage of the boosting circuit as an internal voltage; a control circuit for controlling the internal voltage generating circuit; and a writing circuit for applying the internal voltage to the memory cell as a writing voltage when writing data into the memory cell, wherein the control circuit controls the internal voltage to a first voltage necessary for writing data into the memory cell when writing data into the memory cell, and to a second voltage lower than the first voltage i

Abstract: A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.

Abstract: A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.

Abstract: A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.

Abstract: A semiconductor integrated circuit device with a power-on detecting circuit, wherein the power-on detecting circuit includes: first and second power supply terminals between which an external power supply voltage is to be supplied; a first diode circuit having a first resistor and a first diode connected in series between the first and second power supply terminals, an interconnect node between the first resistor and first diode serving as a first voltage detecting node; a second diode circuit having second and third resistors and a second diode connected in series between the first and second power supply terminals, the second diode having a current drivability larger than the first diode, an interconnect node between the second and third resistors serving as a second voltage detecting node; and a first comparator for detecting a voltage of the second voltage detecting node becoming higher than that of the first voltage detecting node to output a power-on signal.

Abstract: A semiconductor integrated circuit device with a power-on detecting circuit, wherein the power-on detecting circuit includes: first and second power supply terminals between which an external power supply voltage is to be supplied; a first diode circuit having a first resistor and a first diode connected in series between the first and second power supply terminals, an interconnect node between the first resistor and first diode serving as a first voltage detecting node; a second diode circuit having second and third resistors and a second diode connected in series between the first and second power supply terminals, the second diode having a current drivability larger than the first diode, an interconnect node between the second and third resistors serving as a second voltage detecting node; and a first comparator for detecting a voltage of the second voltage detecting node becoming higher than that of the first voltage detecting node to output a power-on signal.

Abstract: A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.

Abstract: A semiconductor integrated circuit device with a power-on detecting circuit, wherein the power-on detecting circuit includes: first and second power supply terminals between which an external power supply voltage is to be supplied; a first diode circuit having a first resistor and a first diode connected in series between the first and second power supply terminals, an interconnect node between the first resistor and first diode serving as a first voltage detecting node; a second diode circuit having second and third resistors and a second diode connected in series between the first and second power supply terminals, the second diode having a current drivability larger than the first diode, an interconnect node between the second and third resistors serving as a second voltage detecting node; and a first comparator for detecting a voltage of the second voltage detecting node becoming higher than that of the first voltage detecting node to output a power-on signal.

Abstract: A semiconductor integrated circuit device with a power-on detecting circuit, wherein the power-on detecting circuit includes: first and second power supply terminals between which an external power supply voltage is to be supplied; a first diode circuit having a first resistor and a first diode connected in series between the first and second power supply terminals, an interconnect node between the first resistor and first diode serving as a first voltage detecting node; a second diode circuit having second and third resistors and a second diode connected in series between the first and second power supply terminals, the second diode having a current drivability larger than the first diode, an interconnect node between the second and third resistors serving as a second voltage detecting node; and a first comparator for detecting a voltage of the second voltage detecting node becoming higher than that of the first voltage detecting node to output a power-on signal.