Patents by Inventor Masaki Maeda
Masaki Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240148839Abstract: Disclosed is a serum albumin-thioredoxin fusion body which is improved in the activity thereof and is stable with respect to the activity. The serum albumin-thioredoxin fusion body is provided, which is characterized in that the thioredoxin is a modified from in which at least a cysteine residue located at position 73 from the N-terminal of an amino acid sequence for the thioredoxin or located at a position equivalent to the position 73 is substituted by another amino acid residue. the modified serum albumin-thioredoxin fusion body is superior in the activity and stability thereof, is reduced in immunogenicity and has superior safety compared with a fusion body in which the thioredoxin is non-modified form.Type: ApplicationFiled: March 15, 2022Publication date: May 9, 2024Inventors: Junichi MATSUDA, Kento NISHIDA, Masaki HIRASHIMA, Toru MARUYAMA, Hiroshi WATANABE, Hitoshi MAEDA
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Publication number: 20240150882Abstract: To provide a galvanized steel sheet having high strength, specifically, a tensile strength of 1,150 MPa or more, and excellent resistance spot weldability, a base steel sheet has a defined chemical composition, an amount of diffusible hydrogen in the base steel sheet is 0.20 mass ppm or less, and surface roughness Ra of the galvanized steel sheet is 0.6 ?m or less.Type: ApplicationFiled: February 25, 2022Publication date: May 9, 2024Applicant: JFE STEEL CORPORATIONInventors: Satoshi MAEDA, Hiromi YOSHITOMI, Masaki KOBA, Nao KAWABE, Tatsuya NAKAGAITO, Katsuya HOSHINO, Hiroshi MATSUDA
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Publication number: 20240152013Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer iType: ApplicationFiled: January 19, 2024Publication date: May 9, 2024Inventors: Yoshihito HARA, Tohru DAITOH, Hajime IMAI, Teruyuki UEDA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
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Patent number: 11927860Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer iType: GrantFiled: April 11, 2022Date of Patent: March 12, 2024Assignee: SHARP DISPLAY TECHNOLOGY CORPORATIONInventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Teruyuki Ueda, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata
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Publication number: 20240025486Abstract: A protector structure for an underfloor component includes an underfloor component that is a high-voltage component or a fuel tank disposed under a floor of a vehicle, a boarding and alighting step disposed further laterally outward with respect to the underfloor component, and a protection member disposed between the underfloor component and the boarding and alighting step. The protection member includes a contact wall that laterally faces the boarding and alighting step and that is inclined laterally inward as the contact wall extends downward.Type: ApplicationFiled: July 12, 2023Publication date: January 25, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Katsuya WATANABE, Junichi Abe, Masaki Maeda
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Publication number: 20230365768Abstract: A coating liquid for producing a gas barrier laminate, the coating liquid containing a carboxyl group-containing polymer (a), polyvalent metal-containing particles (b), a surfactant (c), a specific silicon-containing compound (d), and an organic solvent (e). In the coating liquid: the equivalence ratio (bt/at) of the product (bt) of the number of moles and the valency of the polyvalent metal contained in the polyvalent metal-containing particles (b) relative to the number of moles (at) of carboxyl groups contained in the carboxyl group-containing polymer (a) is 0.45 or more and 0.9 or less; and the molar ratio (dt/at) of the number of moles (dt) of the silicon-containing compound (d) relative to the number of moles (at) of the carboxyl groups is 0.7% or more and 7.5% or less.Type: ApplicationFiled: July 17, 2023Publication date: November 16, 2023Applicant: TOPPAN INC.Inventors: Seiji TAKIZAWA, Masaki MAEDA
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Patent number: 11804498Abstract: The present invention has an object to reduce the number of necessary masks to reduce manufacturing cost. A method of manufacturing a display device includes: forming electrodes or first lines; forming a first insulating film covering the electrodes or the first lines; forming a second insulating film covering the first insulating film; collectively forming first contact holes through the first insulating film and the second insulating film so as to expose parts of the electrodes or parts of the first lines; planarizing a surface of the second insulating film; and forming a first conductive layer to be connected from the surface of the second insulating film to the exposed parts of the electrodes or the exposed parts of the first lines via the first contact holes.Type: GrantFiled: May 21, 2020Date of Patent: October 31, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tatsuya Kawasaki, Tohru Daitoh, Hajime Imai, Hideki Kitagawa, Yoshihito Hara, Masaki Maeda, Yoshiharu Hirata, Teruyuki Ueda
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Publication number: 20230317739Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer.Type: ApplicationFiled: April 4, 2023Publication date: October 5, 2023Inventors: Hajime IMAI, Tohru DAITOH, Yoshihito HARA, Tetsuo KIKUCHI, Teruyuki UEDA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
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Publication number: 20230307465Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.Type: ApplicationFiled: May 18, 2023Publication date: September 28, 2023Inventors: Hajime IMAI, Tohru DAITOH, Teruyuki UEDA, Yoshihito HARA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA, Tetsuo KIKUCHI
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Publication number: 20230303788Abstract: A gas barrier laminate including a substrate, an inorganic deposition layer containing an inorganic oxide, and a coating layer, arranged in this order, the coating layer contains a carboxy group-containing polymer (a), polyvalent metal-containing particles (b), a surfactant (c), and a silicon-containing compound (d), the silicon-containing compound (d) is at least one selected from the group consisting of a silane coupling agent having certain structures, hydrolysates thereof, and condensates thereof, a molar ratio (dt)/(at) represented by [the number of moles (dt) of the silicon-containing compound (d)/the number of moles (at) of carboxy groups of the carboxy group-containing polymer (a)] is 0.15% or more and 6.10% or less, and the coating layer has a film thickness of 230 nm or more and 600 nm or less, with (d) in the molar ratio (d)/(a) is the mass of the silicon-containing compound (d) converted into an equivalent mass of the silane coupling agent.Type: ApplicationFiled: May 18, 2023Publication date: September 28, 2023Applicant: TOPPAN INC.Inventor: Masaki MAEDA
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Patent number: 11695020Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.Type: GrantFiled: December 11, 2020Date of Patent: July 4, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Hajime Imai, Tohru Daitoh, Teruyuki Ueda, Yoshihito Hara, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata, Tetsuo Kikuchi
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Patent number: 11668987Abstract: A display device includes a switching element having a pixel connection portion, a first insulating film having a first pixel contact hole formed therein so as to be in a place overlapping at least a part of the pixel connection portion, a common line, an intermediate electrode composed of the same conducting film as the common line, disposed to overlap the first pixel contact hole, and connected to the pixel connection portion, a common electrode not connected to the intermediate electrode but connected to the common line, a second insulating film having a second pixel contact hole formed therein so as to be in a place overlapping at least a part of the intermediate electrode, and a pixel electrode disposed so that at least a part of the pixel electrode overlaps the second pixel contact hole.Type: GrantFiled: April 28, 2021Date of Patent: June 6, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshihito Hara, Hajime Imai, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata, Tohru Daitoh
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Publication number: 20230115899Abstract: A gas barrier laminate in which separation between a coating layer having gas barrier properties and a layer adjacent to the coating layer is less likely to occur. A coating solution for producing a gas barrier laminate contains a carboxyl group-containing polymer (A), polyvalent metal-containing particles (B), a surfactant (C), an organic solvent (D), and at least one silicon-containing compound (E) selected from the group consisting of a silane coupling agent represented by the following general formula (1), a silane coupling agent represented by the following general formula (2), hydrolysates thereof, and condensates thereof, wherein the mass ratio of the silicon-containing compound (E) to the carboxyl group-containing polymer (A) is 0.5% or more. Si(OR1)3Z1 . . . (1); Si(R2)(OR3)2Z2 . . . (2). (R1 and R3 are alkyl groups having 1 to 6 carbon atoms, R2 is a methyl group, and Z1 and Z2 are a group containing an epoxy group.Type: ApplicationFiled: December 14, 2022Publication date: April 13, 2023Applicant: TOPPAN INC.Inventors: Tetsuya OKANO, Masaki MAEDA
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Publication number: 20230082232Abstract: An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.Type: ApplicationFiled: September 6, 2022Publication date: March 16, 2023Inventors: Tatsuya KAWASAKI, Tohru DAITOH, Hajime IMAI, Teruyuki UEDA, Masaki MAEDA, Yoshiharu HIRATA, Yoshihito HARA
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Publication number: 20230048009Abstract: Deterioration of gas barrier properties due to sedimentation of aggregates in a coating liquid is decreased or minimized. A coating liquid for producing a gas barrier laminate contains a carboxy group-containing polymer, polyvalent metal-containing particles, a high molecular weight dispersant with an acidic group, and an organic solvent, and has a pH in a range of 4 to 6 at 25° C.Type: ApplicationFiled: October 12, 2022Publication date: February 16, 2023Applicant: TOPPAN INC.Inventors: Masaki MAEDA, Tetsuya OKANO
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Patent number: 11569324Abstract: An active matrix substrate includes a first TFT and a second TFT, in which the first TFT includes a first oxide semiconductor layer and a first gate electrode arranged on a part of the first oxide semiconductor layer with a first gate insulating layer interposed therebetween, the first gate insulating layer has a layered structure including a first insulating film and a second insulating film arranged on the first insulating film, the second TFT includes a second oxide semiconductor layer having a higher mobility than the first oxide semiconductor layer and a second gate electrode arranged on a part of the second oxide semiconductor layer with a second gate insulating layer interposed therebetween, and the second gate insulating layer includes the second insulating film and does not include the first insulating film, and the second TFT further includes a lower insulating layer including the first insulating film arranged between the second oxide semiconductor layer and a substrate.Type: GrantFiled: June 4, 2021Date of Patent: January 31, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Hajime Imai, Tohru Daitoh, Teruyuki Ueda, Yoshihito Hara, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata
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Publication number: 20220342246Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer iType: ApplicationFiled: April 11, 2022Publication date: October 27, 2022Inventors: Yoshihito HARA, Tohru DAITOH, Hajime IMAI, Teruyuki UEDA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
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Patent number: 11476282Abstract: An active matrix substrate includes gate bus lines; source bus lines; a lower insulating layer; an oxide semiconductor TFT; and a pixel electrode, in which the oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode, a source electrode, and a first ohmic conductive portion that is coupled to the oxide semiconductor layer and the source electrode, the lower insulating layer includes a source opening portion exposing at least a portion of the source electrode, the first ohmic conductive portion is disposed on the lower insulating layer and in the source opening portion and is in direct contact with at least the portion of the source electrode in the source opening portion, and the first region of the oxide semiconductor layer is in direct contact with an upper surface of the first ohmic conductive portion.Type: GrantFiled: August 4, 2020Date of Patent: October 18, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Masaki Maeda, Tatsuya Kawasaki, Hideki Kitagawa, Yoshiharu Hirata
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Patent number: 11468961Abstract: A semiconductor memory device includes a data bus terminal group for outputting read data to an external device or inputting write data from an external device, a first terminal from or into which 1-bit data is output or input, a DBI circuit that executes a Data Bus Inversion (DBI) function, an error detection circuit that detects an internal error, and an information superimposing circuit that superimposes predetermined output information onto the 1-bit data to be output from the first terminal and the read data to be output from the data bus terminal group. The predetermined output information includes first output information indicating whether or not an output bit pattern of the data bus terminal group is inverted, and second output information indicating whether or not an internal error has been detected by the error detection circuit.Type: GrantFiled: July 6, 2020Date of Patent: October 11, 2022Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kazuhito Tanaka, Masaki Maeda
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Publication number: 20220283674Abstract: An in-cell touch panel includes a plurality of source lines, a source redundant line, a touch sensor line formed in the same layer as the plurality of source lines or the source redundant line, an organic insulating layer formed in a layer above the touch sensor line, and a common electrode formed in a layer above the organic insulating layer. A contact hole in which part of the common electrode is arranged is formed in the organic insulating layer above the touch sensor line, and the common electrode is connected to the touch sensor line via the contact hole.Type: ApplicationFiled: March 1, 2022Publication date: September 8, 2022Inventors: MASAKI MAEDA, TOHRU DAITOH, HAJIME IMAI, YOSHIHITO HARA, TERUYUKI UEDA, YOSHIHARU HIRATA, TATSUYA KAWASAKI