Patents by Inventor Masaki Maeda

Masaki Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12276893
    Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer i
    Type: Grant
    Filed: January 19, 2024
    Date of Patent: April 15, 2025
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Teruyuki Ueda, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata
  • Publication number: 20250026550
    Abstract: A gas barrier laminate includes a substrate layer containing a resin, an inorganic oxide layer, and a gas barrier coat layer in this order. The gas barrier coat layer is a cured article containing a water-soluble polymer, a first silicon compound of a silicon alkoxide in formula (1) below, and a second silicon compound of a silicon alkoxide in formula (2) below. The ratio of the water-soluble polymer to the water-soluble polymer and the second silicon compound is 55 to 95% by mass, and the ratio of the first silicon compound to the first silicon compound and the second silicon compound is more than 0% by mass and 89% by mass or less. Si(OR1)4 . . . (1) (R2Si(OR3)3)n . . . (2) (in formulas (1) and (2) above, R1 and R3 each denote an alkyl group, and R2 denotes an organic functional group; n represents an integer equal to or greater than 1).
    Type: Application
    Filed: October 7, 2024
    Publication date: January 23, 2025
    Applicant: TOPPAN HOLDINGS INC.
    Inventor: Masaki MAEDA
  • Publication number: 20240414940
    Abstract: A display device includes: a base substrate; a thin-film transistor layer provided on the base substrate and having a first metal layer containing a copper film; and a light-emitting element layer provided on the thin-film transistor layer, and including a plurality of pixel electrodes, a plurality of light-emitting functional layers, and a common electrode, all of which are sequentially stacked on top of another and corresponding to a plurality of subpixels. A terminal unit includes a plurality of terminals formed of a same material as, and arranged in a same layer as, the first metal layer. Each of the pixel electrodes is formed of a second metal layer containing a silver film. On each of the terminals, a terminal protective layer formed of a transparent conductive film is provided.
    Type: Application
    Filed: December 6, 2021
    Publication date: December 12, 2024
    Inventors: Masaki MAEDA, Hajime IMAI, Yoshiharu HIRATA, Teruyuki UEDA, Tatsuya KAWASAKI, Tohru DAITOH
  • Patent number: 12142614
    Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: November 12, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hajime Imai, Tohru Daitoh, Teruyuki Ueda, Yoshihito Hara, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata, Tetsuo Kikuchi
  • Publication number: 20240337885
    Abstract: An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.
    Type: Application
    Filed: June 18, 2024
    Publication date: October 10, 2024
    Inventors: Tatsuya KAWASAKI, Tohru DAITOH, Hajime IMAI, Teruyuki UEDA, Masaki MAEDA, Yoshiharu HIRATA, Yoshihito HARA
  • Publication number: 20240329748
    Abstract: The present technology relates to an information processing system and a control method that enable a gesture-based operation to be performed more easily. An information processing system according to one aspect of the present technology detects an action of a user, displays a GUI related to an operation using a gesture on the basis of detection of a first gesture made by the user, identifies an operation presented on the GUI on the basis of a second gesture made following the first gesture, and executes a control command corresponding to the identified operation. The present technology is applicable to an operation of a TV to which a camera device is coupled.
    Type: Application
    Filed: March 3, 2022
    Publication date: October 3, 2024
    Applicant: Sony Group Corporation
    Inventors: Masaki Maeda, Takeshi Matsuzawa, Shimon Sakai, Erika Ohno, Yohei Nakajima
  • Publication number: 20240304851
    Abstract: A manufacturing method disclosed herein includes: a step of constructing a battery assembly in which an electrode body and a non-aqueous electrolytic solution are accommodated in a battery case, the electrode body including a positive electrode and a negative electrode laminated on each other across a separator; a step of initially charging the battery assembly; a high-temperature holding step of holding the battery assembly after subjected to the initial charging step at a high temperature equal to or greater than 40° C.; an ordinary-temperature holding step of holding the battery assembly at an ordinary temperature for a duration exceeding 3 hours after the high-temperature holding step; and a degassing step of pressing the battery assembly after subjected to the ordinary-temperature holding step in a laminating direction of the electrode body and releasing the battery assembly.
    Type: Application
    Filed: February 16, 2024
    Publication date: September 12, 2024
    Inventors: Masaki MAEDA, Masahide MIYAKE, Junichi YOGO
  • Publication number: 20240257774
    Abstract: In each of unit circuits that constitute a shift register, a first conduction terminal of a second thin-film transistor that controls the output of an output signal serving as a scanning signal is given a second input clock signal having a amplitude larger than the amplitude of a first input clock signal that is given to a first conduction terminal of a first thin-film transistor that controls the output of an output signal serving as a control signal for controlling another unit circuit. The channel length of the second thin-film transistor is set to be greater than the channel length of the first thin-film transistor, so that the breakdown voltage of the second thin-film transistor is higher than the breakdown voltage of the first thin-film transistor.
    Type: Application
    Filed: December 5, 2023
    Publication date: August 1, 2024
    Inventors: Jun NISHIMURA, Yoshihito Hara, Masaki Maeda, Yoshiharu Hirata, Hideki Kitagawa, Masamitsu Yamanaka, Tohru Daitoh
  • Patent number: 12044943
    Abstract: An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: July 23, 2024
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Tatsuya Kawasaki, Tohru Daitoh, Hajime Imai, Teruyuki Ueda, Masaki Maeda, Yoshiharu Hirata, Yoshihito Hara
  • Publication number: 20240152013
    Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer i
    Type: Application
    Filed: January 19, 2024
    Publication date: May 9, 2024
    Inventors: Yoshihito HARA, Tohru DAITOH, Hajime IMAI, Teruyuki UEDA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
  • Patent number: 11927860
    Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer i
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 12, 2024
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Teruyuki Ueda, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata
  • Publication number: 20240025486
    Abstract: A protector structure for an underfloor component includes an underfloor component that is a high-voltage component or a fuel tank disposed under a floor of a vehicle, a boarding and alighting step disposed further laterally outward with respect to the underfloor component, and a protection member disposed between the underfloor component and the boarding and alighting step. The protection member includes a contact wall that laterally faces the boarding and alighting step and that is inclined laterally inward as the contact wall extends downward.
    Type: Application
    Filed: July 12, 2023
    Publication date: January 25, 2024
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Katsuya WATANABE, Junichi Abe, Masaki Maeda
  • Publication number: 20230365768
    Abstract: A coating liquid for producing a gas barrier laminate, the coating liquid containing a carboxyl group-containing polymer (a), polyvalent metal-containing particles (b), a surfactant (c), a specific silicon-containing compound (d), and an organic solvent (e). In the coating liquid: the equivalence ratio (bt/at) of the product (bt) of the number of moles and the valency of the polyvalent metal contained in the polyvalent metal-containing particles (b) relative to the number of moles (at) of carboxyl groups contained in the carboxyl group-containing polymer (a) is 0.45 or more and 0.9 or less; and the molar ratio (dt/at) of the number of moles (dt) of the silicon-containing compound (d) relative to the number of moles (at) of the carboxyl groups is 0.7% or more and 7.5% or less.
    Type: Application
    Filed: July 17, 2023
    Publication date: November 16, 2023
    Applicant: TOPPAN INC.
    Inventors: Seiji TAKIZAWA, Masaki MAEDA
  • Patent number: 11804498
    Abstract: The present invention has an object to reduce the number of necessary masks to reduce manufacturing cost. A method of manufacturing a display device includes: forming electrodes or first lines; forming a first insulating film covering the electrodes or the first lines; forming a second insulating film covering the first insulating film; collectively forming first contact holes through the first insulating film and the second insulating film so as to expose parts of the electrodes or parts of the first lines; planarizing a surface of the second insulating film; and forming a first conductive layer to be connected from the surface of the second insulating film to the exposed parts of the electrodes or the exposed parts of the first lines via the first contact holes.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: October 31, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tatsuya Kawasaki, Tohru Daitoh, Hajime Imai, Hideki Kitagawa, Yoshihito Hara, Masaki Maeda, Yoshiharu Hirata, Teruyuki Ueda
  • Publication number: 20230317739
    Abstract: The active matrix substrate includes a plurality of oxide semiconductor TFTs supported by a substrate. Each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer including a channel region, a lower electrode positioned between the oxide semiconductor layer and the substrate, and an insulating layer positioned between the oxide semiconductor layer and the lower electrode. The insulating layer has a layered structure including a lower layer, an upper layer positioned between the lower layer and the oxide semiconductor layer, and an intermediate layer positioned between the lower layer and the upper layer. The upper layer is a silicon oxide layer, the intermediate layer contains at least silicon and nitrogen, and the lower layer contains at least silicon, nitrogen, and oxygen. A hydrogen desorption amount in the lower layer is larger than a hydrogen desorption amount in the intermediate layer.
    Type: Application
    Filed: April 4, 2023
    Publication date: October 5, 2023
    Inventors: Hajime IMAI, Tohru DAITOH, Yoshihito HARA, Tetsuo KIKUCHI, Teruyuki UEDA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA
  • Publication number: 20230303788
    Abstract: A gas barrier laminate including a substrate, an inorganic deposition layer containing an inorganic oxide, and a coating layer, arranged in this order, the coating layer contains a carboxy group-containing polymer (a), polyvalent metal-containing particles (b), a surfactant (c), and a silicon-containing compound (d), the silicon-containing compound (d) is at least one selected from the group consisting of a silane coupling agent having certain structures, hydrolysates thereof, and condensates thereof, a molar ratio (dt)/(at) represented by [the number of moles (dt) of the silicon-containing compound (d)/the number of moles (at) of carboxy groups of the carboxy group-containing polymer (a)] is 0.15% or more and 6.10% or less, and the coating layer has a film thickness of 230 nm or more and 600 nm or less, with (d) in the molar ratio (d)/(a) is the mass of the silicon-containing compound (d) converted into an equivalent mass of the silane coupling agent.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 28, 2023
    Applicant: TOPPAN INC.
    Inventor: Masaki MAEDA
  • Publication number: 20230307465
    Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 28, 2023
    Inventors: Hajime IMAI, Tohru DAITOH, Teruyuki UEDA, Yoshihito HARA, Masaki MAEDA, Tatsuya KAWASAKI, Yoshiharu HIRATA, Tetsuo KIKUCHI
  • Patent number: 11695020
    Abstract: An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: July 4, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hajime Imai, Tohru Daitoh, Teruyuki Ueda, Yoshihito Hara, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata, Tetsuo Kikuchi
  • Patent number: 11668987
    Abstract: A display device includes a switching element having a pixel connection portion, a first insulating film having a first pixel contact hole formed therein so as to be in a place overlapping at least a part of the pixel connection portion, a common line, an intermediate electrode composed of the same conducting film as the common line, disposed to overlap the first pixel contact hole, and connected to the pixel connection portion, a common electrode not connected to the intermediate electrode but connected to the common line, a second insulating film having a second pixel contact hole formed therein so as to be in a place overlapping at least a part of the intermediate electrode, and a pixel electrode disposed so that at least a part of the pixel electrode overlaps the second pixel contact hole.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: June 6, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihito Hara, Hajime Imai, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata, Tohru Daitoh
  • Publication number: 20230115899
    Abstract: A gas barrier laminate in which separation between a coating layer having gas barrier properties and a layer adjacent to the coating layer is less likely to occur. A coating solution for producing a gas barrier laminate contains a carboxyl group-containing polymer (A), polyvalent metal-containing particles (B), a surfactant (C), an organic solvent (D), and at least one silicon-containing compound (E) selected from the group consisting of a silane coupling agent represented by the following general formula (1), a silane coupling agent represented by the following general formula (2), hydrolysates thereof, and condensates thereof, wherein the mass ratio of the silicon-containing compound (E) to the carboxyl group-containing polymer (A) is 0.5% or more. Si(OR1)3Z1 . . . (1); Si(R2)(OR3)2Z2 . . . (2). (R1 and R3 are alkyl groups having 1 to 6 carbon atoms, R2 is a methyl group, and Z1 and Z2 are a group containing an epoxy group.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 13, 2023
    Applicant: TOPPAN INC.
    Inventors: Tetsuya OKANO, Masaki MAEDA