Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

Abstract: The present invention provides a method of manufacturing a TFT substrate, in which method a data signal line is separated into upper and lower regions at a separating point(Q) that is not around above a scan signal line but in a region where an i-layer and an n+ layer formed on a gate insulating film are removed away in a flattened region of a gate insulating film.

Abstract: In order to reuse configuration information in a dynamic reconfiguration arithmetic circuit, data lines, address lines, a mask register and the like are required as hardware resources for rewriting only configuration information of dynamic reconfiguration arithmetic cells needed to be changed. However, this results in an increase in area of the arithmetic circuit. According to the present invention, a shift register is the only hardware resource in the dynamic reconfiguration arithmetic block for changing the configuration information. The shift register is structured by connecting in series storage units corresponding one-to-one with each arithmetic cell. An output from the end terminal of the shift register and an output of the configuration information storage unit are input to the configuration information selector, and an output of the configuration information selector is connected to the front of the shift register. The cell address counter counts up from 0 and increments one at a time.

Abstract: When compression encoding processing of an image is performed in units of macroblocks using pipeline structure, application of the skip mode or the like according to MPEG4AVC to compression encode an encoding target block requires motion vectors and the like of adjacent blocks of the encoding target block. However, depending on the structure of the pipeline stages, the motion vectors and the like may not be determined. In such cases, the skip mode cannot be applied to compression encode the encoding target block. The present invention aims to solve this problem and (i) calculates all motion information candidates, of the encoding target block, corresponding to all motion information selectable by a previous block of the encoding target block, and (ii) selects, as the motion information of the encoding target block in the skip mode, the motion information corresponding to the motion information determined for the previous block.

Abstract: An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each cycle, operation control information for controlling an operation of a processor element of a first order, and then generates an instruction to the processor element of the first order in accordance with the operation control information and the acquired instruction, and also generates, in each cycle, operation control information for controlling an operation of each processor element of a next order and onwards, in accordance with operation control information generated for controlling an operation of a processor element of an immediately preceding order, and then generates an instruction to each processor element of the next order and onwards, in accordance with the operation control information generated and the acquired instruction.

Abstract: A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit sequentially decodes an instruction, and performs a control based on the instruction. When decoding a coprocessor operation instruction to request the coprocessor to perform an operation, which includes operands designating a type of an operation to be performed by the coprocessor, a first register storing data to be used for the operation, and a second register to store data obtained by the operation, the control unit requests the coprocessor to perform the designated type of operation by using a content in the first register, and causes the second register to store a result of the operation.

Abstract: In order to reuse configuration information in a dynamic reconfiguration arithmetic circuit, data lines, address lines, a mask register and the like are required as hardware resources for rewriting only configuration information of dynamic reconfiguration arithmetic cells needed to be changed. However, this results in an increase in area of the arithmetic circuit. According to the present invention, a shift register is the only hardware resource in the dynamic reconfiguration arithmetic block for changing the configuration information. The shift register is structured by connecting in series storage units corresponding one-to-one with each arithmetic cell. An output from the end terminal of the shift register and an output of the configuration information storage unit are input to the configuration information selector, and an output of the configuration information selector is connected to the front of the shift register. The cell address counter counts up from 0 and increments one at a time.

Abstract: A length of each pocket of a cage in a circumferential direction is smaller than the sum of an outer diameter of a roller and a free length of a coil spring. The cage can rotate relative to an inner ring having cam surfaces in accordance with revolution of the rollers in an overload-applied condition, and the cage can not rotate in a direction opposite to a direction of revolution of the rollers in the overload-applied condition.

Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

Abstract: Objects of the present invention are to provide a method for molding polymers to be able to mold products each of which has an outer shape transferred accurately from the shape of the inside of a mold, exhibits high dimensional accuracy and is uniform in the thickness of its surface skin layer and the expansion ratio in its foamed inside. A molten polymer 60 is injected into a cavity 30 and simultaneously gas is pressed to the inside of the molten polymer 60 to contact the polymer close to the surface of the mold, and then gas is exhausted while maintaining the shape inside the mold, to thereby mold a polymer formed product in which a surface skin layer 61 and a foamed inside 62 having cushioning property are formed in one piece.

Abstract: A moving picture conversion apparatus converts first moving image data encoded in accordance with a first motion compensated prediction method into second moving picture data that has a same format as data encoded in accordance a second motion compensated prediction method. The moving picture conversion apparatus determines whether a relationship between a block in the second motion compensation method and an image used as a reference image with respect to the block confirms with a condition. When the relationship is determined to conform with the condition, the moving picture conversion apparatus performs encoding using a motion vector or vectors of the first moving image data corresponding to the block.

Abstract: A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit sequentially decodes an instruction, and performs a control based on the instruction. When decoding a coprocessor operation instruction to request the coprocessor to perform an operation, which includes operands designating a type of an operation to be performed by the coprocessor, a first register storing data to be used for the operation, and a second register to store data obtained by the operation, the control unit requests the coprocessor to perform the designated type of operation by using a content in the first register, and causes the second register to store a result of the operation.

Abstract: Disclosed are oil-extended 1,2-polybutadiene containing an extender oil in a specific amount based on 1,2-polybutadiene and a production method thereof, and a composition further containing another (co)polymer, a foaming agent, a crosslinking agent, a softening agent and other additives. The resulting oil-extended 1,2-polybutadiene and the composition thereof has excellent functions characterizing conventional 1,2-polybutadiene and is further excellent in wear resistance, fluidity (processability), coloring properties (high distinctness of images), flexibility, attachability and the like, so that they can be applied to various formed articles, shoe sole materials and laminate having high performances.

Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

Abstract: Objects of the present invention are to provide a method for molding polymers to be able to mold products each of which has an outer shape transferred accurately from the shape of the inside of a mold, exhibits high dimensional accuracy and is uniform in the thickness of its surface skin layer and the expansion ratio in its foamed inside.