Abstract: A process for forming an array of FATMOS transistors serving as memory cells of a NAND cell type EEPROM. A multi-layered structure is provided on a substrate with two stacked conductive layers insulated by an intermediate insulative layer, the first or inner conductive layer being insulated by a first insulative layer from the substrate, the second or outer conductive layer being covered with a second insulative layer. The second insulative layer is etched to define a first array of etched layer portions. A photoresist layer is deposited and etched to define a second array of layer portions, each of which is positioned between two neighboring ones of the first array of layer portions. The multi-layered structure is etched with the first and second layer portions being as a mask, to thereby form an array of a plurality of pairs of insulated gate electrodes above the substrate.

Abstract: A plurality of electrically erasable programmable read-only memories or EEPROMs are associated with a controller LSI. Each EEPROM includes an array of floating-gate tunneling memory cell transistors arranged in rows and columns. When a sub-array of memory cell transistors providing a one-page data is selected for programming, the controller LSI performs a write/verify operation as follows the electrically written state after the programming of the selected memory cell transistors is verified by checking their threshold values for variations, and when any potentially insufficient cell transistor remains among them, the rewrite operation using a predetermined write voltage for a predetermined period of time is repeated so that the resultant write state may come closer to a satisfiable reference state. Each rewrite/verify operation is performed by applying the write voltage to the insufficient cell transistor for a predetermined period of time.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A NOR operation is performed on the address bit by bit by a NOR circuit, and when the final address in a page is detected from the result of the NOR operation by a final address detection circuit, a program starting circuit executes data writing to a memory cell. This can ensure detection of the final address in a page without using a counter circuit. It is therefore possible to simplify the structure of the final address detection circuit and reduce the circuit area occupying in a semiconductor memory device.

Abstract: A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

Abstract: An EEPROM includes an array of memory cells divided into a plurality of memory blocks in a semiconductor well region in a substrate. Each block includes series arrays of FATMOS transistors each acting as one memory cell, wherein binary information may be stored in a selected cell transistor by causing carriers to tunnel between the floating gate thereof and the well region. In each block, word lines are connected to the control gates of cell transistors; control lines are to select transistors provided in the series arrays of cell transistors, with which bit lines are associated. A block-erase operation is performed such that a desired one of the memory blocks is selected for erase, while forcing the remaining memory blocks to remain non-erased. To do this, a first voltage is applied to those of the word lines of the selected block, while applying a second voltage to the remaining word lines of the non-selected blocks, the control lines of all the blocks, and the well region.

Abstract: A NAND-cell type electrically erasable and programmable read only memory includes an array of rows and columns of memory cells associated with parallel bit lines on a semiconductive substrate. Each memory cell essentially consists of a floating-gate field effect transistor having a floating gate and an insulated control gate. The memory cell array is divided into a plurality of cell blocks, each of which includes NAND cell sections each including a predetermined number of a series-connected memory cell transistors. A redundancy cell section is provided which includes an array of redundancy memory cells containing at least one spare cell block. A row redundancy circuit is connected to a row decoder, and is responsive to an address buffer. The redundancy circuit replaces a defective block containing a defective memory cell or cells with the spare cell block.

Abstract: The present invention provides a semiconductor memory device capable of reducing its current consumption, controlling the generation of noise, and increasing in access using a precharge voltage applied to a precharge circuit. In the semiconductor memory device, a precharge circuit is connected to a pair of data input/output lines, and includes a MOS transistor connected between one of the data input/output lines and a node of a precharge voltage and a MOS transistor connected between the other data input/output line and a node of the precharge voltage. The gates of the MOS transistors are supplied with control signals so that the MOS transistors are turned on when the data input/output lines are precharged. A MOS transistor is connected to the data input/output lines for equalizing them. The precharge voltage is set to half of a value obtained by subtracting the threshold voltage of the MOS transistor from the power supply voltage.

Abstract: A NAND cell type electrically erasable programmable read-only memory has NAND cell units. Each NAND cell unit has a series array of floating gate type metaloxide semiconductor field effect transistors as memory cell transistors. The first-stage memory cell transistor is connected at its gate to a corresponding bit line via a first select transistor The last-stage memory cell transistor is connected at its source to a common source line by means of a second select transistor. The common source line is connected with a test circuit to be used for measuring the distribution of threshold values of the memory cell transistors in the erasing state. The test circuit temporarily applies the common source line with a positive bias voltage of a predetermined potential level so that the potential of the control gate of a selected memory cell transistor is set at to 0 volt. As a result, the threshold value of the EEPROM in the erasing state can be measured without using any negative potential.

Abstract: An electrically erasable programmable read-only memory has memory cell blocks, each of which has NAND type cell units associated with the bit lines respectively. Each cell unit has a series-circuit of floating gate type memory cell transistors and a selection transistor provided between the corresponding bit line and the series-circuit of memory cell transistors. A row decoder is provided in common to the memory cell blocks, for generating an "H" level voltage which is supplied to a selection gate control line connected to the selection transistor and to a selected word line or lines in a cell unit. A voltage boost circuit is provided for every memory cell block, for causing the "H" level voltage to increase up to a preselected potential level which is high enough to render the cell transistors conductive. The voltage boost circuit includes a first booster section for the selection gate control line, and a second section for the word lines.

Abstract: A NAND cell type EEPROM has parallel data transmission lines formed above a substrate, and a memory cell section including a plurality of NAND type cell units containing a NAND type cell unit that is associated with a certain bit line of the bit lines. This NAND type cell unit has a series-circuit of a preselected number of data storage transistors with control gates, and a selection transistor. A substrate voltage-stabilizing layer is insulatively provided above the substrate and positioned in the field area in adjacent to the certain bit line. The conductive layer is connected to the substrate by a contact portion so that the substrate voltage can be constantly set to a preselected voltage potential of a fixed value during the NAND type cell unit is being subjected to the write and erase modes.

Abstract: An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage.

Abstract: An electrically erasable programmable read-only memory has memory cell blocks, each of which has NAND type cell units associated with the bit lines respectively. Each cell unit has a series-circuit of floating gate type memory cell transistors and a selection transistor provided between the corresponding bit line and the series-circuit of memory cell transistors. A row decoder is provided in common to the memory cell blocks, for generating an "H" level voltage which is supplied to a selection gate control line connected to the selection transistor and to a selected word line or lines in a cell unit. A voltage boost circuit is provided for every memory cell block, for causing the "H" level voltage to increase up to a preselected potential level which is high enough to render the cell transistors conductive. The voltage boost circuit includes a first booster section for the selection gate control line, and a second section for the word lines.

Abstract: An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line.

Abstract: A NAND cell type EEPROM has a substrate, parallel bit lines formed above the substrate, and a memory cell section including an array of NAND type cell units associated with the same corresponding bit line. Each of the NAND type cell units has a series-circuit of eight data storage transistors and at least one selection transistor. Each data storage transistor has a floating gate for storing carriers injected thereinto by tunneling and a control gate respectively connected to word lines. A control gate driver circuit is provided in common for all the NAND type cell units that are assisted with the same bit line. Transfer gates are connected between the common driver circuit and the NAND cell units.

Abstract: An electrically erasable programmable read-only memory with a NAND cell structure has parallel bit lines, and memory cells defining NAND cell blocks, each of which has a series-circuit of memory cell transistors. Each transistor has a floating gate and a control gate. Parallel word lines are connected to the control gates of the cell transistors. The first, second and third intermediate voltages are used in the data write mode: the first voltage is lower than the "H" level voltage and higher than the "L" level voltage; the second and third voltages are higher than the first voltage and lower than the "H" level voltage.

Abstract: An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence.

Abstract: An erasable programmable read-only memory with NAND cell structure is disclosed which includes NAND cell blocks each of which has a selection transistor connected to a corresponding bit line and a series array of memory cell transistors. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data erase mode all the memory cells are simultaneously erased by applying a "H" level potential to the control gates of the memory cells and a "L" level potential to the bit lines. Prior to such a simultaneous erase, charges are removed from charge accumulation layers of the memory cells so that the threshold values of the memory cells are initialized. The threshold initialization is performed on the series-arrayed memory cell transistors in the NAND cell block in sequence.

Abstract: The semiconductor integrated circuit comprises a semiconductor substrate having a circuit region, a pad formed at the surface of the semiconductor substrate and forming a PN junction with the semiconductor substrate, and first and second electrodes. Each electrode contacts the semiconductor region such that the contacting regions of the electrodes face each other with a ring shaped region between.

Abstract: A highly-integrated semiconductor dynamic random-acess memory is disclosed wherein a reference voltage-generating circuit is connected by voltage-transmission lines to a row-address buffer and a column-address buffer. The reference voltage-generating circuit receives a power-supply voltage and generates first and second reference voltages which are different, by different values, from an ordinary reference potential level. These reference voltages are supplied to the address buffers through the voltage-transmission lines. The first and second reference voltages are adjusted to compensate for a potential deviation which occurs on the voltage-transmission lines. Therefore, even when either reference voltage fluctuates due to an increase in the coupling capacitance between the substrate of the dynamic random-access memory, on the one hand, and the voltage-transmission lines, on the other, both address buffers are prevented from malfunctioning.