Patents by Inventor Masaki Okamoto

Masaki Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10224234
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: March 5, 2019
    Assignee: Sony Corporation
    Inventor: Masaki Okamoto
  • Publication number: 20180246258
    Abstract: Influence of chipping in case of dicing a plurality of stacked substrates is reduced. Provided is a semiconductor device where a substrate, in which a groove surrounding a pattern configured with a predetermined circuit or part is formed, is stacked. The present technology can be applied to, for example, a stacked lens structure where through-holes are formed in each substrate and lenses are disposed in inner sides of the through-holes, a camera module where a stacked lens structure and a light-receiving device are incorporated, a solid-state imaging device where a pixel substrate and a control substrate are stacked, and the like.
    Type: Application
    Filed: July 19, 2016
    Publication date: August 30, 2018
    Inventors: Toshiaki SHIRAIWA, Masaki OKAMOTO, Hiroyasu MATSUGAI, Hiroyuki ITOU, Suguru SAITO, Keiji OHSHIMA, Nobutoshi FUJII, Hiroshi TAZAWA, Minoru ISHIDA
  • Patent number: 10062974
    Abstract: A connector 10 disclosed by this specification is a connector 10 to be mounted on a casing 1 of a device by being inserted into a mounting hole 2 provided in the casing 1 and includes a terminal 40 connected to a wire W, a housing 20 having the terminal 40 mounted therein, and an intermediate terminal 30 made of metal, mounted in the housing 20 and disposed between the terminal 40 and a mating terminal 4 in the casing 1. A fastened component (nut 5) disposed in the casing 1 and to be fastened to a fastening component (bolt B), the mating terminal 4, the intermediate terminal 30 and the terminal 40 are arranged side by side in a fastening direction, and the terminal 40 and the mating terminal 4 are connected via the intermediate terminal 30 by being collectively fastened by the fastening component and the fastened component.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: August 28, 2018
    Assignee: Sumitomo Wiring Systems, Ltd
    Inventors: Masaki Okamoto, Masaaki Kobayashi, Yasushi Okayasu, Masaru Kitagawa
  • Publication number: 20180158803
    Abstract: There is provided a semiconductor device and an electronic apparatus that comprises a semiconductor device, the semiconductor device including a first chip, a second chip that is bonded onto a first surface side of the first chip, a through electrode that is formed to penetrate from a second surface side of the first chip to a second wiring layer on the second semiconductor base substrate, and an insulation layer that is disposed between the through electrode and a semiconductor base substrate in the first chip.
    Type: Application
    Filed: February 2, 2018
    Publication date: June 7, 2018
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda
  • Publication number: 20180114807
    Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.
    Type: Application
    Filed: March 11, 2016
    Publication date: April 26, 2018
    Applicant: Sony Corporation
    Inventors: HAJIME YAMAGISHI, KIYOTAKA TABUCHI, MASAKI OKAMOTO, TAKASHI OINOUE, MINORU ISHIDA, SHOTA HIDA, KAZUTAKA YAMANE
  • Patent number: 9922961
    Abstract: There is provided a semiconductor device and an electronic apparatus that comprises a semiconductor device, the semiconductor device including a first chip, a second chip that is bonded onto a first surface side of the first chip, a through electrode that is formed to penetrate from a second surface side of the first chip to a second wiring layer on the second semiconductor base substrate, and an insulation layer that is disposed between the through electrode and a semiconductor base substrate in the first chip.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: March 20, 2018
    Assignee: Sony Corporation
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda
  • Publication number: 20180076534
    Abstract: A connector 10 disclosed by this specification is a connector 10 to be mounted on a casing 1 of a device by being inserted into a mounting hole 2 provided in the casing 1 and includes a terminal 40 connected to a wire W, a housing 20 having the terminal 40 mounted therein, and an intermediate terminal 30 made of metal, mounted in the housing 20 and disposed between the terminal 40 and a mating terminal 4 in the casing 1. A fastened component (nut 5) disposed in the casing 1 and to be fastened to a fastening component (bolt B), the mating terminal 4, the intermediate terminal 30 and the terminal 40 are arranged side by side in a fastening direction, and the terminal 40 and the mating terminal 4 are connected via the intermediate terminal 30 by being collectively fastened by the fastening component and the fastened component.
    Type: Application
    Filed: April 6, 2016
    Publication date: March 15, 2018
    Inventors: Masaki Okamoto, Masaaki Kobayashi, Yasushi Okayasu, Masaru Kitagawa
  • Patent number: 9887486
    Abstract: A waterproof connector is a connectable to a device-side connector (80) and has a housing (30) with a fitting (34) that can fit into an outer tube (82) of the device-side connector (80). A connector seal ring (36) is fit on an outer peripheral surface of the fitting (34) and is held resiliently in close contact with the outer tube (82) and the fitting (34). Individual terminal accommodating portions (37) are provided in the housing (30) and can fit into device-side cavities (84) provided in the device-side connector (80). Individual seal rings (38) are fitted on outer peripheral surfaces of the individual terminal accommodating portions (37) and are held resiliently in close contact with inner peripheral surfaces of the device-side cavities (84) and the individual terminal accommodating portions (37). The connector seal rings (36) and the individual seal rings are displaced in a front-rear direction.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: February 6, 2018
    Assignee: SUMITOMO WIRING SYSTEMS, LTD.
    Inventor: Masaki Okamoto
  • Publication number: 20170288336
    Abstract: A waterproof connector is a connectable to a device-side connector (80) and has a housing (30) with a fitting (34) that can fit into an outer tube (82) of the device-side connector (80). A connector seal ring (36) is fit on an outer peripheral surface of the fitting (34) and is held resiliently in close contact with the outer tube (82) and the fitting (34). Individual terminal accommodating portions (37) are provided in the housing (30) and can fit into device-side cavities (84) provided in the device-side connector (80). Individual seal rings (38) are fitted on outer peripheral surfaces of the individual terminal accommodating portions (37) and are held resiliently in close contact with inner peripheral surfaces of the device-side cavities (84) and the individual terminal accommodating portions (37). The connector seal rings (36) and the individual seal rings are displaced in a front-rear direction.
    Type: Application
    Filed: August 4, 2015
    Publication date: October 5, 2017
    Inventor: Masaki Okamoto
  • Patent number: 9754990
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: September 5, 2017
    Assignee: Sony Corporation
    Inventor: Masaki Okamoto
  • Publication number: 20170236745
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventor: Masaki Okamoto
  • Publication number: 20170069604
    Abstract: There is provided a semiconductor device and an electronic apparatus that comprises a semiconductor device, the semiconductor device including a first chip, a second chip that is bonded onto a first surface side of the first chip, a through electrode that is formed to penetrate from a second surface side of the first chip to a second wiring layer on the second semiconductor base substrate, and an insulation layer that is disposed between the through electrode and a semiconductor base substrate in the first chip.
    Type: Application
    Filed: November 17, 2016
    Publication date: March 9, 2017
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda
  • Patent number: 9524925
    Abstract: There is provided a method for manufacturing a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: December 20, 2016
    Assignee: Sony Corporation
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda
  • Patent number: 9482676
    Abstract: The present invention provides a method for detecting idiopathic interstitial pneumonia, which comprises measuring the expression level of a periostin gene or the amount of a periostin protein in a biological sample. Thereby, a method for detecting idiopathic interstitial pneumonia using a marker is provided.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: November 1, 2016
    Assignees: SAGA UNIVERSITY, KURUME UNIVERSITY
    Inventors: Kenji Izuhara, Shoichiro Ohta, Hiroshi Shiraishi, Hisamichi Aizawa, Tomoaki Hoshino, Masaki Okamoto
  • Patent number: 9431448
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 30, 2016
    Assignee: SONY CORPORATION
    Inventor: Masaki Okamoto
  • Publication number: 20160247746
    Abstract: There is provided a method for manufacturing a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.
    Type: Application
    Filed: April 12, 2016
    Publication date: August 25, 2016
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda
  • Publication number: 20160211298
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Application
    Filed: March 30, 2016
    Publication date: July 21, 2016
    Inventor: Masaki Okamoto
  • Patent number: 9343392
    Abstract: There is provided a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 17, 2016
    Assignee: Sony Corporation
    Inventors: Satoru Wakiyama, Masaki Okamoto, Yutaka Ooka, Reijiroh Shohji, Yoshifumi Zaizen, Kazunori Nagahata, Masaki Haneda
  • Publication number: 20160086997
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 24, 2016
    Inventor: Masaki Okamoto
  • Patent number: 9236412
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: January 12, 2016
    Assignee: SONY CORPORATION
    Inventor: Masaki Okamoto