Abstract: A pig rearing support apparatus includes: an acquirer configured to acquire image data of an image captured by a camera unit installed facing a pen in which sows are raised in a group; a detector configured to detect mounting behavior of the sows based on the image of the image data; and a count processor configured to count the number of times the mounting behavior is detected within a preset observation period. Such a pig rearing support apparatus can inform a breeder at the right time without involving excessive cost or labor whether there is any sow that shows estrus symptoms among sows being raised in a group in a pen.

Abstract: Provided is a technology that allows estrus of a sow to be accurately determined without relying on experience or in intuition of an observer. An estrus determination device for a sow includes a measurement unit that measures, per unit time, a frequency of standing up and lying down of a sow raised in a stall and a determination unit that determines estrus of the sow on the basis of a plurality of frequencies repetitively measured by the measurement unit over a set given period.

Abstract: Provided is a technology that allows easy evaluation of a degree of growth of pigs raised in a group instead of guiding the pigs one by one to a cage. A growth evaluation device includes an extraction unit that extracts, from an image captured by a camera disposed to face a pen in which the plurality of pigs are raised in the group, a buttock image having buttocks of one of the pigs facing forward, an arithmetic unit that arithmetically determines a buttock width from the buttock image, and an evaluation unit that evaluates the degree of growth of all the plurality of pigs on the basis of a prescribed number or more of the buttock widths arithmetically determined by the arithmetic unit.

Abstract: A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. The time determination signal generation circuit is configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined, and the timing circuit is configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged.

Abstract: A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. The time determination signal generation circuit is configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined, and the timing circuit is configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged.

Abstract: A conductive fine particle, which is used for conductive connection between fine electrodes and tends not to give rise to a crack in the solder layer or disconnection caused by breakage in the connection interface between an electrode and the conductive fine particle even with a drop impact and the like, and tends not to have fatigue even after repetitive heating and cooling; an anisotropic conductive material obtained by using the conductive fine particle; and a conductive connection structure.

Abstract: A grid computing system includes a plurality of nodes for processing a plurality of jobs, and a management apparatus for managing the plurality of the nodes. Each of the nodes is switchable between a standby and an active status, respectively. And the management apparatus including, a job request unit for allotting a plurality of requests of jobs to any of the nodes in an active state, a prediction unit for predicting the number of the nodes in the active state optimal for predicted amount of jobs requested from the exterior at a future time when a predetermined time period lapses from the present time, and a controller for controlling switching of the nodes between the standby and active so as to control the predicted number of the nodes to start switching before the future time.

Abstract: It is an object of the present invention to provide: a conductive fine particle, which is used for conductive connection between fine electrodes and tends not to give rise to a crack in the solder layer or disconnection caused by breakage in the connection interface between an electrode and the conductive fine particle even with a drop impact and the like, and tends not to have fatigue even after repetitive heating and cooling; an anisotropic conductive material obtained by using the conductive fine particle; and a conductive connection structure. The present invention relates to a conductive fine particle, which comprises a solder layer containing tin and being formed on a surface of a resin fine particle, with nickel adhered to a surface of the solder layer, and contains 0.0001 to 5.0% by weight of the nickel with respect to a total of a metal contained in the solder layer and the nickel adhered to the surface of the solder layer.

Abstract: An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced.

Abstract: To terminate startup of an application on an ASP side irrespective of checking on a user side whether or not the application is in the middle of processing. A monitoring device includes means monitoring an operating status of an information processing device for providing a service by starting up an information processing program to a user terminal specified by user identifying information, means judging whether or not the operating status of the information processing device meets a predetermined condition, means terminating the startup of the information processing program if the operating status meets the predetermined condition, and means notifying the user terminal of the termination of the startup of the information processing program.

Abstract: A semiconductor memory has a memory cell array having dynamic memory cells. An access control circuit accesses the memory cells in response to an access command which is supplied externally. A refresh control circuit generates, during a test mode, a test refresh request signal in synchronization with the access command so as to execute a refresh operation of the memory cells when a refresh mask signal is at an invalid level. Also, the refresh control circuit prohibits generation of the test refresh request signal when the refresh mask signal is at a valid level. The test refresh request signal is generated or prohibited from being generated according to the level of the refresh mask signal. Thus, only a refresh operation needed for a test can be executed, and hence test efficiency can be improved.

Abstract: A semiconductor integrated circuit includes a semiconductor substrate, one or more wells formed in the semiconductor substrate, one or more diffusion layers formed in the one or more wells, a plurality of interconnects formed in an interconnect layer, the one or more diffusion layers and the plurality of interconnects being connected in series to provide a coupling between a first potential and a second potential, and a comparison circuit coupled to one of the interconnects set at a third potential between the first potential and the second potential, and configured to compare the third potential with a reference potential, wherein a first interconnect of the plurality of interconnects that is set to the first potential is connected to at least a first well of the one or more wells and connected to a first diffusion layer of the one or more diffusion layers that is formed in the first well.

Abstract: In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals; a first MOS capacitor in which a gate of a p-channel MOS field effect transistor is connected to the low reference potential terminal, and a source and a drain are connected to the high reference potential terminal; and a first signal wiring connected to the gate via a parasitic capacitor and a signal in the low reference potential is supplied at the time of starting the power supply.

Abstract: An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced.

Abstract: A semiconductor integrated circuit includes a semiconductor substrate, one or more wells formed in the semiconductor substrate, one or more diffusion layers formed in the one or more wells, a plurality of interconnects formed in an interconnect layer, the one or more diffusion layers and the plurality of interconnects being connected in series to provide a coupling between a first potential and a second potential, and a comparison circuit coupled to one of the interconnects set at a third potential between the first potential and the second potential, and configured to compare the third potential with a reference potential, wherein a first interconnect of the plurality of interconnects that is set to the first potential is connected to at least a first well of the one or more wells and connected to a first diffusion layer of the one or more diffusion layers that is formed in the first well.

Abstract: In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals; a first MOS capacitor in which a gate of a p-channel MOS field effect transistor is connected to the low reference potential terminal, and a source and a drain are connected to the high reference potential terminal; and a first signal wiring connected to the gate via a parasitic capacitor and a signal in the low reference potential is supplied at the time of starting the power supply.

Abstract: A semiconductor memory has a memory cell array having dynamic memory cells. An access control circuit accesses the memory cells in response to an access command which is supplied externally. A refresh control circuit generates, during a test mode, a test refresh request signal in synchronization with the access command so as to execute a refresh operation of the memory cells when a refresh mask signal is at an invalid level. Also, the refresh control circuit prohibits generation of the test refresh request signal when the refresh mask signal is at a valid level. The test refresh request signal is generated or prohibited from being generated according to the level of the refresh mask signal. Thus, only a refresh operation needed for a test can be executed, and hence test efficiency can be improved.

Abstract: A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.

Abstract: To terminate startup of an application on an ASP side irrespective of checking on a user side whether or not the application is in the middle of processing. A monitoring device includes means monitoring an operating status of an information processing device for providing a service by starting up an information processing program to a user terminal specified by user identifying information, means judging whether or not the operating status of the information processing device meets a predetermined condition, means terminating the startup of the information processing program if the operating status meets the predetermined condition, and means notifying the user terminal of the termination of the startup of the information processing program.

Abstract: In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals; a first MOS capacitor in which a gate of a p-channel MOS field effect transistor is connected to the low reference potential terminal, and a source and a drain are connected to the high reference potential terminal; and a first signal wiring connected to the gate via a parasitic capacitor and a signal in the low reference potential is supplied at the time of starting the power supply.