Abstract: A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.

Abstract: A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.

Abstract: A charge management apparatus includes a module measuring a usage quantity of an information processing device when providing a user specified by user identifying information with a service based on an program specified by program identifying information on the information processing device specified by a device identifying information, a module measuring a usage quantity of the program when providing the service, a module calculating a device charge from a unit usage charge of the information processing device referred to based on the device identifying information and from a usage quantity of the information processing device, a module calculating a program charge from a unit usage charge of the program referred to based on the program identifying information and from a usage quantity of the program, and a module calculating a service charge for providing the service from the device charge and from the program charge.

Abstract: In a data transfer method for transfer of data by a first information processing terminal device to a second information processing terminal device connected to the first information processing terminal device via a signal line, the first information processing terminal device calculates a maximum required time according to the amount of data for transfer and transfer performance information relating to the connection of the first information processing terminal device with the second information processing terminal device; upon initiating the data transfer processing, the first information processing terminal device continuously confirms that the data transfer processing is in state of execution from the time of initiation of the data transfer processing until the maximum required time has elapsed; and if, when the maximum required time has elapsed, the data transfer processing initiated is confirmed to be continuing, the first information processing terminal device forcibly ends the data transfer processing

Abstract: In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals; a first MOS capacitor in which a gate of a p-channel MOS field effect transistor is connected to the low reference potential terminal, and a source and a drain are connected to the high reference potential terminal; and a first signal wiring connected to the gate via a parasitic capacitor and a signal in the low reference potential is supplied at the time of starting the power supply.

Abstract: Provided are a predetermined usage amount acquisition unit acquiring predetermined usage amount information within a predetermined period about the computer resources from the user terminals, a real usage amount calculation unit calculating real usage amount information indicating amount of actual usage of the user terminals within the predetermined period, and a charge calculation unit calculating, when calculating a charge imposed on the user terminals on the basis of the predetermined usage amount information and the real usage amount information, respectively a charge for a real usage amount equal to or larger than the predetermined usage amount and a charge for a real usage amount equal to or smaller than the predetermined usage amount in the whole usage amount by applying amount of money per different unit usage amount.

Abstract: A logical circuit receives first and second input signals in which a period of a first logic level partially overlaps, and outputs first and second output signals in which a period of the first logic level does not overlap. The logical circuit comprises a first unit which changes a phase of the first output signal from a second logic level to the first logic level when a change of the first input signal from the second logic level to the first logic level is detected. A second unit changes a phase of the second output signal from the first logic level to the second logic level when the second input signal is detected as being at the first logic level at a time of detection of the change of the first input signal.

Abstract: A semiconductor memory device is capable of simultaneously reading data and refreshing data and checking whether a data restoring function is operating normally. A data inputting circuit receives data inputted from an external circuit. A parity generating circuit generates parity data from the data input from the data inputting circuit. A memory stores the data input from the data inputting circuit and the parity data generated by the parity generating circuit. A refreshing circuit refreshes the memory. A reading circuit reads the data from the memory. A restoring circuit restores data to be refreshed by the refreshing circuit from other data read normally and corresponding parity data, while the reading circuit is reading data. A data outputting circuit outputs the data read by the reading circuit and the data restored by the restoring circuit. A parity outputting circuit directly reads and outputs the parity data stored in the memory.

Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

Abstract: A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

Abstract: A plurality of memory blocks is allocated the same address spaces to write the same data therein, and is operable independently of one another. One of the memory blocks is selected as a refresh block that performs a refresh operation, in response to a refresh command, while another one of the memory blocks is selected as a read block that performs a read operation, in response to a read command. Then, the plurality of memory blocks performs read operations at different timings so that the read operations overlap one another. Therefore, the semiconductor memory can receive read commands at intervals each of which is shorter than the execution time of a single read operation. As a result, externally supplied read commands can be responded to at high speed, and the data transmission rate during read operation can be improved.

Abstract: A phase adjustment circuit delays an external clock signal to generate an adjusted clock signal. A phase comparator compares phases of the external clock signal and the adjusted clock signal, and outputs a phase adjustment signal for adjusting a delay time of the phase adjustment circuit. A data output circuit outputs read data to a data terminal in synchronization with the adjusted clock signal. A data input circuit receives write data supplied to the data terminal, in synchronization with the adjusted clock signal. When performing input of the write data and output of the read data successively, switching control between the input operation of the write data and the output operation of the read data only has to be completed within one clock cycle. The clock cycle can thus be reduced to the time required for the switching control. Consequently, maximum frequency of the external clock signal can be increased.

Abstract: A phase adjustment circuit delays an external clock signal to generate an adjusted clock signal. A phase comparator compares phases of the external clock signal and the adjusted clock signal, and outputs a phase adjustment signal for adjusting a delay time of the phase adjustment circuit. A data output circuit outputs read data to a data terminal in synchronization with the adjusted clock signal. A data input circuit receives write data supplied to the data terminal, in synchronization with the adjusted clock signal. When performing input of the write data and output of the read data successively, switching control between the input operation of the write data and the output operation of the read data only has to be completed within one clock cycle. The clock cycle can thus be reduced to the time required for the switching control. Consequently, maximum frequency of the external clock signal can be increased.

Abstract: A semiconductor memory device includes a plurality of memory blocks, each of which is refreshed independently of one another, m (m>1) data pins, each of which continuously receives or outputs n (n>1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, m×n data bus lines on which the n data pieces are expanded in parallel with respect to each of the m data pins, m address selection lines which are connected to m respective blocks of the memory blocks corresponding to the m respective data pins, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the m respective blocks and resulting in the n data pieces being input/output to/from the corresponding one of the m respective blocks.

Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

Abstract: A semiconductor memory device includes a plurality of memory blocks, each of which is refreshed independently of one another, m (m>1 ) data pins, each of which continuously receives or outputs n (n>1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, m×n data bus lines on which the n data pieces are expanded in parallel with respect to each of the m data pins, m address selection lines which are connected to m respective blocks of the memory blocks corresponding to the m respective data pins, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the m respective blocks and resulting in the n data pieces being input/output to/from the corresponding one of the m respective blocks, and a parity data comparison circuit which performs a parity check on m data pieces read from the m respective blocks corresponding to the m respective data pins a

Abstract: A semiconductor memory device is capable of simultaneously reading data and refreshing data and checking whether a data restoring function is operating normally. A data inputting circuit receives data inputted from an external circuit. A parity generating circuit generates parity data from the data input from the data inputting circuit. A memory stores the data input from the data inputting circuit and the parity data generated by the parity generating circuit. A refreshing circuit refreshes the memory. A reading circuit reads the data from the memory. A restoring circuit restores data to be refreshed by the refreshing circuit from other data read normally and corresponding parity data, while the reading circuit is reading data. A data outputting circuit outputs the data read by the reading circuit and the data restored by the restoring circuit. A parity outputting circuit directly reads and outputs the parity data stored in the memory.

Abstract: One aspect of the present invention is that, when the memory is in the non-power-down state, the supply of clock signals to the data output circuit is limited to the read status after the reception of a read command, and no clock signal supply is performed when either the active status or the write status is in effect. In the best aspect, furthermore, in the read status after the reception of a read command, the supply of clock signals to the data output circuit starts after a number of clock signals corresponding to a set CAS latency following the read command, and stops after a number of clock signals corresponding to a set burst length, after the output of the read out data from the data output circuit starts. Accordingly, even in the non-power-down state, clock signals are only supplied during the time required for the read out data to be actually output from the data output circuit to the outside, whereby it is possible to reduce the number of clock signal supply actions that require large current drive.

Abstract: A semiconductor device includes a device-type switching circuit which determines selection signals A based on fuse-cut conditions in a first mode, and determines selection signals based on control signals supplied thereto in a second mode, and an internal circuit having an operation thereof selected by selection signals from device-type switching circuit.

Abstract: A memory device comprises: a plurality of banks each of which includes an array of memory cells; and at least a first and a second internal power generator, provided for each of the plurality of banks, for generating an internal power source voltage which differs from a voltage supplied by an external power source. If the internal common power source voltage in the memory device is lower than the first voltage when the power is on, the first and the second internal power generators in a plurality of banks are activated so as to rapidly raise the common internal power source voltage. When the common internal power source voltage in the memory device is higher than the first voltage and lower than the second voltage, the second internal power generators in the banks are activated to compensate for a drop in the internal power source voltage, which is caused by current leakage.