Patents by Inventor Masaki Shimada

Masaki Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929201
    Abstract: A surface mount inductor includes a coil including a wound portion and a feeder end portion drawn out from the wound portion, a compact that contains a magnetic powder and that encapsulates the coil, and an external terminal disposed on the compact and connected to the coil. The compact has surfaces including two pressed surfaces, opposing each other in a direction of an axis of the wound portion and formed by being pressed in the direction of the axis, and a non-pressed surface, adjacent to the two surfaces and not pressed. The coil is disposed so that the axis of the wound portion is parallel to a mount surface of the compact. The mount surface is included in the non-pressed surface, the feeder end portion is exposed from the mount surface, and the external terminal is formed on only the non-pressed surface and connected to the feeder end portion.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: March 12, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yuki Kitashima, Masaki Kitajima, Takeo Ohaga, Takeshi Shimada, Yoshiaki Hirama, Daigo Mizumura, Ryota Watanabe, Masato Koike, Yuusuke Morita
  • Patent number: 11821795
    Abstract: A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: November 21, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Yoshio Takazawa, Fumio Tsuchiya, Daisuke Oshida, Naoya Ota, Masaki Shimada, Shinya Konishi
  • Publication number: 20230294501
    Abstract: A mounting structure for a power storage device includes: a power storage device including a power storage stack and a housing case; a floor member; and a rear bracket. The housing case includes a lower case having a rear wall, and an upper case. The floor member is provided with an attachment portion for attaching the rear bracket. The rear bracket includes a front end portion and a rear end portion that is attached to the attachment portion. The power storage stack is disposed inside the housing case to provide a gap between the power storage stack and the rear wall. The front end portion of the rear bracket is fixed to the rear wall to be located between an upper surface and a lower surface of the power storage stack in an up-down direction.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 21, 2023
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaki SHIMADA
  • Patent number: 11697336
    Abstract: A mounting structure for a power storage device includes: a power storage device including a power storage stack and a housing case; a floor member; and a rear bracket. The housing case includes a lower case having a rear wall, and an upper case. The floor member is provided with an attachment portion for attaching the rear bracket. The rear bracket includes a front end portion and a rear end portion that is attached to the attachment portion. The power storage stack is disposed inside the housing case to provide a gap between the power storage stack and the rear wall. The front end portion of the rear bracket is fixed to the rear wall to be located between an upper surface and a lower surface of the power storage stack in an up-down direction.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: July 11, 2023
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaki Shimada
  • Patent number: 11569551
    Abstract: A busbar module includes a case to be attached to a battery assembly, busbars and electric wires having a connection end to be connected to the busbars. The case includes busbar accommodation portions to accommodate the busbars and an electric wire routing groove portion to accommodate the electric wires. The electric wire routing groove portion includes a connection end accommodation portion to accommodate the connection end, an accommodation portion cover and an electric wire lead-out portion configured such that the electric wires are drawn out from the connection end accommodation portion toward a direction. An outer surface of the accommodation portion cover is to form a bottom surface of a routing path configured such that the electric wires drawn out from the connection end accommodation portion extend in the routing path.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: January 31, 2023
    Assignees: YAZAKI CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masamichi Doi, Shinichi Yanagihara, Masaki Shimada, Shuta Ito
  • Publication number: 20220166111
    Abstract: A battery module includes: a plurality of secondary batteries arranged side by side in one direction; a bus bar via which secondary batteries adjacent to each other in the one direction from among the secondary batteries are electrically connected to each other; and a voltage detecting terminal connected to the bus bar. Each of the secondary batteries includes a pair of external terminals. The bus bar includes connecting portions connected to corresponding external terminals, and a protrusion portion protruding upward from the connecting portions. The voltage detection terminal is connected to the protrusion portion.
    Type: Application
    Filed: October 22, 2021
    Publication date: May 26, 2022
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takuya Toyoda, Masaki Shimada, Shuta Ito, Yusuke Kuruma
  • Patent number: 11152665
    Abstract: A vehicle includes a battery pack, seats, and seat rails. The battery pack has a battery case and a battery unit accommodated in the battery case. The seat rails are frame members disposed over the battery pack and fixed to the vehicular body. The battery case has an upper portion with four openings located under the seat rails and formed through both an upper surface of the battery case and a side surface of the battery case.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: October 19, 2021
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaki Shimada
  • Publication number: 20210313655
    Abstract: A busbar module includes a case to be attached to a battery assembly, busbars and electric wires having a connection end to be connected to the busbars. The case includes busbar accommodation portions to accommodate the busbars and an electric wire routing groove portion to accommodate the electric wires. The electric wire routing groove portion includes a connection end accommodation portion to accommodate the connection end, an accommodation portion cover and an electric wire lead-out portion configured such that the electric wires are drawn out from the connection end accommodation portion toward a direction. An outer surface of the accommodation portion cover is to form a bottom surface of a routing path configured such that the electric wires drawn out from the connection end accommodation portion extend in the routing path.
    Type: Application
    Filed: April 5, 2021
    Publication date: October 7, 2021
    Applicants: YAZAKI CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masamichi Doi, Shinichi Yanagihara, Masaki Shimada, Shuta Ito
  • Patent number: 11125628
    Abstract: An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Shinya Konishi, Fumio Tsuchiya, Masaki Shimada
  • Publication number: 20210221212
    Abstract: A mounting structure for a power storage device includes: a power storage device including a power storage stack and a housing case; a floor member; and a rear bracket. The housing case includes a lower case having a rear wall, and an upper case. The floor member is provided with an attachment portion for attaching the rear bracket. The rear bracket includes a front end portion and a rear end portion that is attached to the attachment portion. The power storage stack is disposed inside the housing case to provide a gap between the power storage stack and the rear wall. The front end portion of the rear bracket is fixed to the rear wall to be located between an upper surface and a lower surface of the power storage stack in an up-down direction.
    Type: Application
    Filed: December 30, 2020
    Publication date: July 22, 2021
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaki SHIMADA
  • Patent number: 11068330
    Abstract: The semiconductor device has a module having a predetermined function, an error information acquisition circuit for acquiring error information about an error occurring in the module, a stress acquisition circuit for acquiring a stress accumulated value as an accumulated value of stress applied to the semiconductor device, and an analysis data storage for storing analysis data as data for analyzing the state of the semiconductor device, the error information and the stress accumulated value at the time of occurrence of the error being associated with each other.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: July 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya Ota, Kan Takeuchi, Fumio Tsuchiya, Masaki Shimada, Shinya Konishi, Daisuke Oshida
  • Patent number: 11059949
    Abstract: To provide prepreg having high thermostability and a molded body (fiber reinforced composite) obtained from the prepreg, the prepreg is formed by impregnating a reinforced fiber having an elastic modulus of 100 to 900 GPa with an epoxy resin composition including the following Components A to D so as to have a resin content within a range of 25 to 50 mass %: Component A: an epoxy resin having an oxazolidone ring structure in a molecule thereof; Component B: an epoxy resin that is liquid at 30° C.; Component C: a diblock copolymer having a B-M structure, wherein M is a block including at least 50 mass % of methyl methacrylate, B is a block immiscible with the epoxy resins and the block M, a glass transition temperature of the block B being 20° C. or lower; and Component D: dicyandiamide, or an amine curing agent that is a derivative of dicyandiamide.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: July 13, 2021
    Assignees: NIPPON STEEL CHEMICAL & MATERIAL CO., LTD., Mazda Motor Corporation, Nippon Graphite Fiber Corporation
    Inventors: Koichi Hattori, Yutaka Arai, Masaki Shimada, Tetsuya Sugiyama, Katsuya Himuro, Masanori Honda, Kenji Nishida, Hironobu Takahama
  • Publication number: 20210080330
    Abstract: A semiconductor device according to an embodiment includes a holding circuit including a buffer configured to obtain a heat stress information having a temperature dependency every predetermined period and a stress counter configured to accumulate the heat stress information and hold the accumulated value as a cumulative stress count value, a control circuit including an operation determination threshold value, and a wireless communication circuit. According to the semiconductor device according to the embodiment, while reducing the power consumption, it is possible to wirelessly transmit the cumulative heat stress information.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 18, 2021
    Inventors: Kan TAKEUCHI, Yoshio TAKAZAWA, Fumio TSUCHIYA, Daisuke OSHIDA, Naoya OTA, Masaki SHIMADA, Shinya KONISHI
  • Publication number: 20200102436
    Abstract: To provide prepreg having high thermostability and a molded body (fiber reinforced composite) obtained from the prepreg, the prepreg is formed by impregnating a reinforced fiber having an elastic modulus of 100 to 900 GPa with an epoxy resin composition including the following Components A to D so as to have a resin content within a range of 25 to 50 mass %: Component A: an epoxy resin having an oxazolidone ring structure in a molecule thereof; Component B: an epoxy resin that is liquid at 30° C.; Component C: a diblock copolymer having a B-M structure, wherein M is a block including at least 50 mass % of methyl methacrylate, B is a block immiscible with the epoxy resins and the block M, a glass transition temperature of the block B being 20° C. or lower; and Component D: dicyandiamide, or an amine curing agent that is a derivative of dicyandiamide.
    Type: Application
    Filed: September 24, 2019
    Publication date: April 2, 2020
    Inventors: Koichi Hattori, Yutaka Arai, Masaki Shimada, Tetsuya Sugiyama, Katsuya Himuro, Masanori Honda, Kenji Nishida, Hironobu Takahama
  • Publication number: 20200081757
    Abstract: The semiconductor device has a module having a predetermined function, an error information acquisition circuit for acquiring error information about an error occurring in the module, a stress acquisition circuit for acquiring a stress accumulated value as an accumulated value of stress applied to the semiconductor device, and an analysis data storage for storing analysis data as data for analyzing the state of the semiconductor device, the error information and the stress accumulated value at the time of occurrence of the error being associated with each other.
    Type: Application
    Filed: August 16, 2019
    Publication date: March 12, 2020
    Inventors: Naoya OTA, Kan TAKEUCHI, Fumio TSUCHIYA, Masaki SHIMADA, Shinya KONISHI, Daisuke OSHIDA
  • Patent number: 10566585
    Abstract: A battery pack has a battery unit and a battery case. The battery case includes side frames and an upper frame. The upper frame includes an upper surface portion and a trailing portion that extends downward from an end portion of the upper surface portion. Each of the side frames includes a side surface portion, an intermediate portion that extends from an upper end of the side surface portion inward in the width direction so as to pass below the upper surface portion and faces the upper surface portion in an up-down direction, and a contact portion that extends upward from an end portion of the intermediate portion and is brought into contact with the upper surface portion. The trailing portion includes one or more access openings that are accessible to a space between the upper surface portion and the intermediate portion facing each other in the up-down direction.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: February 18, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaki Shimada
  • Patent number: 10361685
    Abstract: There is to provide a semiconductor device capable of predicting a wear-out failure based on the degradation stress cumulative amount of power supply voltage and environmental temperature imposed on the device, which includes a ring oscillator having a plurality of stages of inverters, and a control circuit that emphasizes the voltage dependency and temperature dependency of an oscillation frequency of the ring oscillator or a control circuit that emphasizes the temperature dependency not the voltage dependency.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: July 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Masaki Shimada, Takeshi Okagaki, Yoshio Takazawa
  • Publication number: 20190181398
    Abstract: A vehicle includes a battery pack, seats, and seat rails. The battery pack has a battery case and a battery unit accommodated in the battery case. The seat rails are frame members disposed over the battery pack and fixed to the vehicular body. The battery case has an upper portion with four openings located under the seat rails and formed through both an upper surface of the battery case and a side surface of the battery case.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 13, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaki SHIMADA
  • Patent number: 10310007
    Abstract: An object of the invention is to provide a semiconductor apparatus capable of achieving conditions that are stricter than the conditions in which the stable operation is guaranteed, without increasing the circuit size. A semiconductor apparatus (10) includes a semiconductor circuit (11); a voltage generator (12) that selects one of at least two types of voltages and applies a power supply voltage, the at least two types of voltages including a normal voltage at which the semiconductor circuit (11) normally operates and a low voltage which is lower than the normal voltage; and a clock generator (13) that supplies the semiconductor circuit (11) with a clock signal having a constant frequency regardless of the power supply voltage.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: June 4, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaki Shimada, Kan Takeuchi
  • Publication number: 20190154518
    Abstract: An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.
    Type: Application
    Filed: September 10, 2018
    Publication date: May 23, 2019
    Inventors: Kan TAKEUCHI, Shinya KONISHI, Fumio TSUCHIYA, Masaki SHIMADA