Abstract: An information processing device include: a memory; and one or more processors which are coupled to the memory, wherein the one or more processors performs a process including verifying a quality of a signal waveform that is propagated through focused wiring on a substrate; and storing information which is used for the verification of the quality of the signal waveform, and wherein the verifying includes determining a relative permittivity of the substrate in a division position of a variation range of the relative permittivity of the substrate such that a variation range of a propagation delay time of the signal waveform corresponding to the variation range of the relative permittivity of the substrate is divided at even intervals; generating an analysis model corresponding to the relative permittivity of the substrate in the determined division position; and performing waveform analysis on the signal waveform using the generated analysis model.

Abstract: An information processing device includes a memory; and one or more processors which are coupled to the memory and configured to performs a process including verifying a quality of a signal waveform that is propagated through focused wiring on a substrate, and storing information which is used for the verification of the quality of the signal waveform, and wherein the verifying includes generating analysis models of a plurality of respective combinations of variations in a plurality of kinds of elements which have an influence on the quality of the signal waveform; calculating impulse-response-waveforms of the plurality of respective combinations using the generated analysis models; calculating the noise amount of the plurality of respective combinations based on the calculated impulse-response-waveforms; selecting a combination, in which the calculated noise amount is the largest, as a worst case in the plurality of combinations; and performing signal waveform-transition-analysis on the selected worst case.

Abstract: An information processing device include: a memory; and one or more processors which are coupled to the memory, wherein the one or more processors performs a process including verifying a quality of a signal waveform that is propagated through focused wiring on a substrate; and storing information which is used for the verification of the quality of the signal waveform, and wherein the verifying includes determining a relative permittivity of the substrate in a division position of a variation range of the relative permittivity of the substrate such that a variation range of a propagation delay time of the signal waveform corresponding to the variation range of the relative permittivity of the substrate is divided at even intervals; generating an analysis model corresponding to the relative permittivity of the substrate in the determined division position; and performing waveform analysis on the signal waveform using the generated analysis model.

Abstract: An information processing device includes a memory; and one or more processors which are coupled to the memory and configured to performs a process including verifying a quality of a signal waveform that is propagated through focused wiring on a substrate, and storing information which is used for the verification of the quality of the signal waveform, and wherein the verifying includes generating analysis models of a plurality of respective combinations of variations in a plurality of kinds of elements which have an influence on the quality of the signal waveform; calculating impulse-response-waveforms of the plurality of respective combinations using the generated analysis models; calculating the noise amount of the plurality of respective combinations based on the calculated impulse-response-waveforms; selecting a combination, in which the calculated noise amount is the largest, as a worst case in the plurality of combinations; and performing signal waveform-transition-analysis on the selected worst case.

Abstract: An antenna designing method, performed by a computer, includes: inputting a first antenna characteristic of an antenna; creating an antenna model that includes the antenna and a matching circuit which is connected to the antenna and is formed by a matching element including parasitic reactance and loss resistance; calculating a second antenna characteristic of the created antenna model by using the first antenna characteristic; determining whether or not the calculated second antenna characteristic satisfies a desired standard value; and displaying a determined result.

Abstract: A semiconductor device includes: a terminal configured to input a signal from a signal source; a receiver configured to receive the signal from the signal source through the terminal; and a terminal circuit configured to be coupled between the terminal and an input end of the receiver, and to suppress reflected wave caused by signal reflection at the receiver, wherein impedance of a wire line connecting the terminal and the input end of the receiver, and direct-current impedance of a resistance component included in the terminal circuit are set lower than impedance of an external wire line connected to the terminal.

Abstract: An electronic component includes a driver that outputs a signal to a reception apparatus; a storage device storing therein reflection information related to a reflected wave that returns to the driver when the signal is reflected back by the reception apparatus; a reflected wave detector that based on the reflection information, determines a measurement period for measuring the reflected wave and that based on the measurement period, measures an arrival time and a peak amplitude of the reflected wave; and a controller that based on the arrival time and the peak amplitude, extracts reflected-wave cancelling information for inhibiting effects of the reflected wave from the reception apparatus and that sets the extracted reflected-wave cancelling information in the driver.

Abstract: A semiconductor device includes: a terminal configured to input a signal from a signal source; a receiver configured to receive the signal from the signal source through the terminal; and a terminal circuit configured to be coupled between the terminal and an input end of the receiver, and to suppress reflected wave caused by signal reflection at the receiver, wherein impedance of a wire line connecting the terminal and the input end of the receiver, and direct-current impedance of a resistance component included in the terminal circuit are set lower than impedance of an external wire line connected to the terminal.

Abstract: A printed circuit board includes a through hole constituted by a hole penetrating through the front and rear surfaces of the printed circuit board. A fabrication method of the printed circuit board, includes applying conductive material plating to the inner wall surface of the hole to form a through hole electrically connecting the front and rear surfaces of the printed circuit board, and removing the conductive material plated on the hole inner wall surface at least at a portion between the front and rear surfaces of the printed circuit board is carried out to thereby fabricate a printed circuit board having a through hole electrically isolates the front surface of the printed circuit board from the rear surface thereof.

Abstract: An electronic component includes a driver that outputs a signal to a reception apparatus; a storage device storing therein reflection information related to a reflected wave that returns to the driver when the signal is reflected back by the reception apparatus; a reflected wave detector that based on the reflection information, determines a measurement period for measuring the reflected wave and that based on the measurement period, measures an arrival time and a peak amplitude of the reflected wave; and a controller that based on the arrival time and the peak amplitude, extracts reflected-wave cancelling information for inhibiting effects of the reflected wave from the reception apparatus and that sets the extracted reflected-wave cancelling information in the driver.

Abstract: A center location of an eye pattern generated by superimposing waveform signal pieces cut out from a waveform signal generated by a simulator is calculated, and an arrangement of a mask as a quality evaluation criterion of the eye pattern on the center location is envisaged to calculate time coordinate values and voltage coordinate values of feature points included in the mask. First feature points not on a time axis is set as processing objects, and a margin in the voltage axis direction is calculated based on the voltage coordinate values of the first feature points and the voltage coordinate values of waveform signal piece parts associated with the first feature points. Second feature points on the time axis is set as processing objects, and a margin in the time axis direction is calculated based on the time coordinate values of the second feature points and the time coordinate values of waveform signal piece parts associated with the second feature points.

Abstract: In order to make it possible to automatically execute a wiring process which satisfies not only a design condition but also design quality relating to an electric characteristic, according to the embodiment, an automatic wiring apparatus includes a design condition changing section for changing a design condition in accordance with priority information regarding the design condition where a wiring process which satisfies the design condition cannot be carried out by a first wiring processing section, a quality allowability decision section for deciding whether or not quality of a wiring region can be allowed where a wiring process which satisfies the design condition after the changing can be executed by a second wiring processing section and an outputting section for outputting a result of the wiring process of the wiring region by the second wiring processing section if it is decided that the quality of the wiring region can be allowed.

Abstract: An equalizer characteristics optimizing method includes acquiring a recovery clock timing from a reception signal; acquiring a predetermined sampling clock timing with respect to the recovery clock timing; latching the reception signal at the recovery clock timing; latching the reception signal at the sampling clock timing; comparing logic values obtained in the latching steps; collecting, after changing a characteristics setting of an equalizer, logic value comparison result data by repeating the recovery clock acquiring step, the acquiring of the sampling clock timing, the latching of the reception signal at the individual clock timings, and the comparing of the logic values, using the changed characteristics setting; and determining an optimum characteristics setting of an equalizer based on the collected logic value comparison result data.

Abstract: A transmission characteristic adjustment device and the like that can carry out circuit adjustment before an error occurs, and has a transmission characteristic with high reliability without generating an error are provided. The device determines existence or non-existence of a difference with respect to confirmed data based on each phase of a multiphase clock, detects a window width in a time axis direction of receiving data based on a result of the determination and a phase of the multiphase clock, and evaluates a setting value of a circuit element of the transmission element or the reception element that has an influence on a receiving waveform based on a fluctuation of the detected window width, and changes the setting value of the circuit element of the transmission element or the reception element based on a result of the evaluation.

Abstract: A center location of an eye pattern generated by superimposing waveform signal pieces cut out from a waveform signal generated by a simulator is calculated, and an arrangement of a mask as a quality evaluation criterion of the eye pattern on the center location is envisaged to calculate time coordinate values and voltage coordinate values of feature points included in the mask. First feature points not on a time axis is set as processing objects, and a margin in the voltage axis direction is calculated based on the voltage coordinate values of the first feature points and the voltage coordinate values of waveform signal piece parts associated with the first feature points. Second feature points on the time axis is set as processing objects, and a margin in the time axis direction is calculated based on the time coordinate values of the second feature points and the time coordinate values of waveform signal piece parts associated with the second feature points.

Abstract: A circuit simulator includes: a DC analysis section which analyses a static stable potential on a transmission circuit if a capacitor which blocks a DC current while allowing an AC current to pass therethrough is connected in series in the line of the transmission circuit; and an initial potential application section which applies, as an initial potential in the simulation, the stable potential obtained by the DC analysis section to an application position on the upstream side of the capacitor in the flow of the signal through the transmission circuit. The simulator also includes a circuit simulation section which performs the simulation of the transmission circuit under the initial potential applied by the initial potential application section.

Abstract: A signal transmission evaluating apparatus acquires cross talk ratio and type categorized by a relationship between the first transmission path and the second transmission path for each of the pins of the second transmission path. The apparatus computes an occupation ratio of the crosstalk for each of the types with respect to all of the crosstalk supplied to the first transmission path in the connector, and computes a noise source output in the second transmission path on the basis of the occupation ratio for each of the types of crosstalk. And the apparatus computes first transmission path loss and second transmission path loss on the basis of the occupation ratio for each of the types of crosstalk, and computes an amount of received noise of the first transmission path on the basis of the noise source output and the first transmission path loss and the second transmission path loss.

Abstract: In order to make it possible to automatically execute a wiring process which satisfies not only a design condition but also design quality relating to an electric characteristic, according to the embodiment, an automatic wiring apparatus includes a design condition changing section for changing a design condition in accordance with priority information regarding the design condition where a wiring process which satisfies the design condition cannot be carried out by a first wiring processing section, a quality allowability decision section for deciding whether or not quality of a wiring region can be allowed where a wiring process which satisfies the design condition after the changing can be executed by a second wiring processing section and an outputting section for outputting a result of the wiring process of the wiring region by the second wiring processing section if it is decided that the quality of the wiring region can be allowed.

Abstract: An equalizer characteristics optimizing method includes acquiring a recovery clock timing from a reception signal; acquiring a predetermined sampling clock timing with respect to the recovery clock timing; latching the reception signal at the recovery clock timing; latching the reception signal at the sampling clock timing; comparing logic values obtained in the latching steps; collecting, after changing a characteristics setting of an equalizer, logic value comparison result data by repeating the recovery clock acquiring step, the acquiring of the sampling clock timing, the latching of the reception signal at the individual clock timings, and the comparing of the logic values, using the changed characteristics setting; and determining an optimum characteristics setting of an equalizer based on the collected logic value comparison result data.

Abstract: A printed circuit board includes a through hole constituted by a hole penetrating through the front and rear surfaces of the printed circuit board. A fabrication method of the printed circuit board, includes applying conductive material plating to the inner wall surface of the hole to form a through hole electrically connecting the front and rear surfaces of the printed circuit board, and removing the conductive material plated on the hole inner wall surface at least at a portion between the front and rear surfaces of the printed circuit board is carried out to thereby fabricate a printed circuit board having a through hole electrically isolates the front surface of the printed circuit board from the rear surface thereof.