Patents by Inventor Masaki Tsukude
Masaki Tsukude has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10515672Abstract: A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.Type: GrantFiled: December 21, 2018Date of Patent: December 24, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinji Tanaka, Yuichiro Ishii, Masaki Tsukude, Yoshikazu Saito
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Publication number: 20190122703Abstract: A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Inventors: Shinji Tanaka, Yuichiro Ishii, Masaki Tsukude, Yoshikazu Saito
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Patent number: 10170161Abstract: A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method including writing first data into a plurality of memory cells, while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a bit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data, and reading the data written into the memory cells.Type: GrantFiled: October 12, 2017Date of Patent: January 1, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinji Tanaka, Yuichiro Ishii, Masaki Tsukude, Yoshikazu Saito
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Publication number: 20180047457Abstract: A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method including writing first data into a plurality of memory cells, while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a bit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data, and reading the data written into the memory cells.Type: ApplicationFiled: October 12, 2017Publication date: February 15, 2018Inventors: Shinji TANAKA, Yuichiro ISHII, Masaki TSUKUDE, Yoshikazu SAITO
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Patent number: 9805821Abstract: A semiconductor memory device includes a memory array including a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs disposed in the columns of the memory cells, a plurality of word lines disposed in the rows of the memory cells, a write drive circuit adapted to transfer data to a bit line pair in a selected column in accordance with write data, and a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column.Type: GrantFiled: August 11, 2016Date of Patent: October 31, 2017Assignee: Renesas Electronics CorporationInventors: Shinji Tanaka, Yuichiro Ishii, Masaki Tsukude, Yoshikazu Saito
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Publication number: 20170092378Abstract: Provided is a semiconductor memory device that is capable of accurately detecting a retention failure of a memory cell. The semiconductor memory device includes a memory array including a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs disposed in the columns of the memory cells, a plurality of word lines disposed in the rows of the memory cells, a write drive circuit adapted to transfer data to a bit line pair in a selected column in accordance with write data, and a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column.Type: ApplicationFiled: August 11, 2016Publication date: March 30, 2017Inventors: Shinji TANAKA, Yuichiro ISHll, Masaki TSUKUDE, Yoshikazu SAITO
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Patent number: 8061895Abstract: There is provided a semiconductor device which can maintain a high tuning accuracy while suppressing a cost increase and suppress an increase in the time required for tuning. There are included, in addition to variable resistors configuring a level shift circuit, an additional resistor coupled between the output node of a VBGR voltage of a BGR circuit and one of the variable resistors and an additional resistor coupled between the other of the variable resistors and a reference voltage. N-channel MOS transistors are coupled in parallel with the additional resistors, respectively.Type: GrantFiled: January 30, 2009Date of Patent: November 22, 2011Assignee: Renesas Electronics CorporationInventor: Masaki Tsukude
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Publication number: 20110199844Abstract: A semiconductor memory device for operating in synchronization with a clock is disclosed. The semiconductor includes a memory array having a plurality of memory cells arranged in rows and columns; and a control circuit performing a control, operation to effect row access processing on a selected row and to effect column access processing on column(s). The control being performed in synchronization with a first clock defined by a time of production of the read signal or the write signal according to an externally applied control signal.Type: ApplicationFiled: April 7, 2011Publication date: August 18, 2011Applicant: Renesas Technology Corp.Inventors: Takeo Miki, Seiji Sawada, Masaki Tsukude
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Patent number: 7983103Abstract: A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.Type: GrantFiled: December 12, 2008Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventor: Masaki Tsukude
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Patent number: 7693004Abstract: This invention discloses a semiconductor memory device having a voltage supply circuit for generating a driver power supply voltage. The voltage supply circuit is provided with a first voltage supply circuit for precharging the driver power supply voltage to a power supply voltage level of a memory cell, and a second voltage supply circuit for supplying a voltage lower than the power supply voltage level of the memory cell as the driver power supply voltage.Type: GrantFiled: January 14, 2008Date of Patent: April 6, 2010Assignee: Renesas Technology Corp.Inventor: Masaki Tsukude
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Publication number: 20090196326Abstract: There is provided a semiconductor device which can maintain a high tuning accuracy while suppressing a cost increase and suppress an increase in the time required for tuning. There are included, in addition to variable resistors configuring a level shift circuit, an additional resistor coupled between the output node of a VBGR voltage of a BGR circuit and one of the variable resistors and an additional resistor coupled between the other of the variable resistors and a reference voltage. N-channel MOS transistors are coupled in parallel with the additional resistors, respectively.Type: ApplicationFiled: January 30, 2009Publication date: August 6, 2009Inventor: Masaki TSUKUDE
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Publication number: 20090091997Abstract: A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.Type: ApplicationFiled: December 12, 2008Publication date: April 9, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Takeo Miki, Seiji Sawada, Masaki TSUKUDE
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Patent number: 7447098Abstract: In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an “H” level and is not reset to an “L” level while the corresponding upper address is designated. This can reduce the standby current.Type: GrantFiled: October 24, 2007Date of Patent: November 4, 2008Assignee: Renesas Technology Corp.Inventor: Masaki Tsukude
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Publication number: 20080258805Abstract: The composing circuit outputs a lower voltage out of voltages output from the constant voltage generation circuit and the dummy pump circuit as a voltage to the sensing circuit. The sensing circuit compares voltages to generate a pump activation signal for activating the pump circuit. Since when an external power supply voltage is a low voltage, the voltage applied to the sensing circuit will be an output voltage of the dummy pump circuit having the same output characteristics as those of the pump circuit in place of the reference voltage, no pump activation signal is generated. As a result, when the external power supply voltage is a low voltage, power consumption can be suppressed without uselessly outputting a pump activation signal.Type: ApplicationFiled: June 17, 2008Publication date: October 23, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventor: Masaki Tsukude
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Publication number: 20080205184Abstract: This invention discloses a semiconductor memory device having a voltage supply circuit for generating a driver power supply voltage. The voltage supply circuit is provided with a first voltage supply circuit for precharging the driver power supply voltage to a power supply voltage level of a memory cell, and a second voltage supply circuit for supplying a voltage lower than the power supply voltage level of the memory cell as the driver power supply voltage.Type: ApplicationFiled: January 14, 2008Publication date: August 28, 2008Inventor: Masaki TSUKUDE
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Patent number: 7397298Abstract: The composing circuit outputs a lower voltage out of voltages output from the constant voltage generation circuit and the dummy pump circuit as a voltage to the sensing circuit. The sensing circuit compares voltages to generate a pump activation signal for activating the pump circuit. Since when an external power supply voltage is a low voltage, the voltage applied to the sensing circuit will be an output voltage of the dummy pump circuit having the same output characteristics as those of the pump circuit in place of the reference voltage, no pump activation signal is generated. As a result, when the external power supply voltage is a low voltage, power consumption can be suppressed without uselessly outputting a pump activation signal.Type: GrantFiled: July 27, 2006Date of Patent: July 8, 2008Assignee: Renesas Technology Corp.Inventor: Masaki Tsukude
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Publication number: 20080062776Abstract: In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an “H” level and is not reset to an “L” level while the corresponding upper address is designated. This can reduce the standby current.Type: ApplicationFiled: October 24, 2007Publication date: March 13, 2008Applicant: RENESAS TECHNOLOGY CORPORATIONInventor: Masaki Tsukude
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Patent number: 7301843Abstract: In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an “H” level and is not reset to an “L” level while the corresponding upper address is designated. This can reduce the standby current.Type: GrantFiled: March 15, 2006Date of Patent: November 27, 2007Assignee: Renesas Technology Corp.Inventor: Masaki Tsukude
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Publication number: 20070024349Abstract: The composing circuit outputs a lower voltage out of voltages output from the constant voltage generation circuit and the dummy pump circuit as a voltage to the sensing circuit. The sensing circuit compares voltages to generate a pump activation signal for activating the pump circuit. Since when an external power supply voltage is a low voltage, the voltage applied to the sensing circuit will be an output voltage of the dummy pump circuit having the same output characteristics as those of the pump circuit in place of the reference voltage, no pump activation signal is generated. As a result, when the external power supply voltage is a low voltage, power consumption can be suppressed without uselessly outputting a pump activation signal.Type: ApplicationFiled: July 27, 2006Publication date: February 1, 2007Inventor: Masaki Tsukude
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Patent number: RE41245Abstract: Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional status memory is provided.Type: GrantFiled: June 9, 2005Date of Patent: April 20, 2010Assignee: Renesas Technology CorporationInventors: Ryu Makabe, Masaki Tsukude, Hirotoshi Sato, Shinichi Kobayashi